Scaling behavior of InAlN/GaN HEMTs on silicon for RF applications

Abstract

Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (I_on/I_off) ratio of 7.28 × 10⁶, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BV_ds) of 36 V, a current/power gain cutoff frequency (f_T/f_max) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (L_g). It presents that a f_T/f_max of 230/327 GHz can be achieved when L_g scales down to 20 nm with the technology developed in the study, and an improved f_T/f_max of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Introduction

InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions due to the low cost and the scaling capability of Si substrate^1,2,3,4. Li et al. demonstrated an InAlN/GaN HEMT on Si with a gate length (L_g) of 55 nm and a source-drain spacing (L_sd) of 175 nm⁵ using n⁺⁺-GaN regrowth source/drain contacts. The device presents a maximum drain current (I_{d, max}) of 2.8 A/mm, a peak extrinsic transconductance (g_m) of 0.66 S/mm, and a current/power gain cutoff frequency (f_T/f_max) of 250/204 GHz. Xie et al. reported that a record f_T of 310 GHz was achieved on an InAlN/GaN HEMT on Si with a 40-nm gate length⁶. Cui et al. demonstrated an 80-nm-gate-length InAlN/GaN HEMT on Si with a record high on/off current (I_on/I_off) ratio of 1.58 × 10⁶, a steep subthreshold swing (SS) of 65 mV/dec, and a f_T of 200 GHz, resulting in a record high f_T × L_g = 16 GHz µm⁷. Chowdhury et al. demonstrated a complementary logic circuit (an inverter) on a GaN-on-Si platform with a record maximum voltage gain of 27 V/V at an input voltage of 0.59 V with V_DD = 5 V⁸. Xie et al. reported an InAlN/GaN HEMT on Si with a f_T of 210 GHz and a three-terminal off-state breakdown voltage (BV_ds) of 46 V, leading to a record high Johnson’s figure-of-merit (JFOM = f_T × BV_ds) of 8.8 THz V⁹. Then et al.reported the high f_T/f_max of 190/300 GHz was achieved on the e-mode high-k InAlN/GaN transistor on 300 mm Si substrate¹⁰.

However, to the best of our knowledge, the highest f_T/f_max of 454/444 GHz and 348/340 GHz were achieved on 20-nm-gate-length AlN/GaN HEMT¹¹ and 27-nm-gate-length InAlN/GaN HEMTs on SiC¹², respectively. Although excellent performances have been demonstrated, InAlN/GaN HEMTs on Si still presents much room to be improved compared with GaN HEMTs on SiC substrate. The InAlN barrier can be grown lattice-matched to GaN when the In component is 17%, which makes it easier grow than AlN on GaN¹³. The InAlN/GaN heterostructure also exhibits higher quantum well polarization-induced charge than AlGaN/GaN heterostructure, resulting in higher channel electron density and drain current^14,15. In addition, compared with AlGaN/GaN, a thinner InAlN barrier in InAlN/GaN HEMTs not only can offer higher frequency performance with an improved device transconductance, but also can suppress the short-channel effect with the reduced gate-to-channel distance^16,17. Hence, exploring the possible limiting factors of InAlN/GaN HEMTs on Si is significant to further improve the device performance. In this paper, high-performance InAlN/GaN HEMTs on Si are demonstrated. The extrinsic and intrinsic parameters of devices with different gate lengths are extracted and the scale behavior of InAlN/GaN HEMTs on Si is predicted. It presents that a f_T/f_max of 230/327 GHz can be achieved when L_g scales down to 20 nm with the technology developed in the study, and an improved f_T/f_max of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMTs with regrowth ohmic contact technology and 30% decreased parasitic capacitance. This confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Experiment

Figure 1a shows the lattice-matched In_0.17Al_0.83N/GaN heterostructure, which is grown on a Si substrate by metalorganic chemical vapor deposition (MOCVD). The epitaxial layer structure consists of a 2-nm GaN cap layer, an 8-nm In_0.17Al_0.83N barrier layer, a 1-nm AlN interlayer, a 15-nm GaN channel layer, a 4-nm In_0.12Ga_0.88N back-barrier layer, and a 2-μm undoped GaN buffer layer¹⁸. The electron sheet concentration and electron mobility measured by Hall measurements were 2.28 × 10¹³ cm⁻² and 1205 cm²/V s, respectively.

Figure 1

(a) Schematic of fabricated InAlN/GaN HEMT; (b) Detailed device fabrication steps; (c) a plan-view scanning electron microscopy (SEM) image of the InAlN/GaN HEMT with a gate head length (L_head) of 400 nm and a source-drain spacing (L_sd) of 600 nm; (d) A SEM image of T-shaped gate structure depicting a gate footprint of 50 nm.

Figure 1b shows the detailed device fabrication steps. The device fabrication started with mesa isolation using Cl₂/CH₄/He/Ar inductively coupled plasma etching. Then Ti/Al/Ni/Au stack was deposited and annealed at 850 °C for 40 s in N₂ to form the alloyed ohmic contacts. The ohmic contact resistance is 0.3 Ω mm. An oxygen plasma treatment was then applied to form the oxide layer on top of the InAlN layer, which can effectively reduce the gate leakage current and improve RF erformance^19,20,21,22. Finally, a Ni/Au T-shaped gate with a gate width (W_g) of 2 × 20 µm was fabricated by electron beam lithography. Figure 1c shows a plan-view scanning electron microscopy (SEM) image of the InAlN/GaN HEMT with a gate head length (L_head) of 400 nm and a source-drain spacing (L_sd) of 600 nm. Figure 1d shows a SEM image of T-shaped gate structure depicting a gate footprint of 50 nm.

Results and discussion

DC performance

The DC current–voltage (I–V) measurements are carried out by using an Agilent B1500A semiconductor parameter analyzer. Figure 2a shows the output characteristic of the InAlN/GaN HEMT with a 50-nm gate length. The device on-resistance (R_on) extracted at gate-source (V_gs) of 0 V and drain-source voltage (V_ds) between 0 and 0.5 V is 1.33 Ω·mm. The gate-to-channel distance t_bar (including a 2-nm GaN, an 8-nm InAlN, and a 1-nm AlN) is 11 nm. Since L_g is 50 nm, the device presents an aspect ratio (L_g/t_bar) of 4.5. Due to the low L_g/t_bar, the short-channel effects (SCEs) start to appear when V_ds is larger than 5 V and V_gs is between − 4 to − 1 V. At V_gs = 1 V, drain current (I_d) in saturation region presents a decrease with increased V_ds, an indication of the thermal effect.

Figure 2

(a) Output characteristic, (b) the extrinsic transconductance g_m, and the transfer characteristic at V_ds = 10 V of the InAlN/GaN HEMT with a 50-nm gate length.

Figure 2b shows the transfer characteristic with the extracted extrinsic transconductance (g_m) of the InAlN/GaN HEMT with a 50-nm gate length at V_ds = 10 V. The maximum saturation drain current (I_{d, max}) is 2.01 A/mm at V_gs = 1 V and V_ds = 10 V. The g_m perk (g_{m, peak}) is 493 mS/mm. To the best of our knowledge, the record high I_{d, max} of 2.8 A/mm and g_m,peak of 660 mS/mm were achieved on a 55-nm-gate-length InAlN/GaN HEMT on Si with regrowth technology and L_sd of 175 nm⁵. The lower I_d and g_m,peak in this study result from the regrowth-free technology and the larger source-drain spacing (L_sd = 600 nm).

Figure 3a shows the transfer and gate current (I_g) characteristics in semi-log scale of the InAlN/GaN HEMT with a 50-nm gate length at V_ds = 5 V and 10 V, respectively. At V_ds = 10 V, the device off-current (I_off) is 2.76 × 10^–7 A/mm and the I_on/I_off ratio is 7.28 × 10⁶, which are higher than the record reported values (I_off of 7.12 × 10^–7 A/mm and I_on/I_off ratio of 1.58 × 10⁶) achieved from the InAlN/GaN HEMT on Si⁷. An average subthreshold swing (SS) of 72 mV/dec over more than two orders of I_d is extracted from the transfer curve. The drain-induced barrier lowering (DIBL) of 88 mV/V is extracted at I_d = 10 mA/mm between V_ds = 10 V and V_ds = 5 V, which is the lowest value among the reported GaN HEMTs on Si. The lowest DIBL value suggests a suppressed SCEs for the sub-100 nm gate-length device. Figure 3b shows the off-state three-terminal breakdown characteristic of the 50-nm InAlN/GaN HEMT measured at V_gs = − 8 V. The device features a BV_ds of 36 V at a drain leakage current of 1 mA/mm.

Figure 3

(a) The transfer and gate current characteristics in semi-log scale at V_ds = 10 V and 5 V, (b) the I_d and I_g as a function of V_ds at V_gs = − 8 V of the InAlN/GaN HEMT with a 50-nm gate length. A BV_ds of 36 V was determined.

RF performance

The device RF performance is measured with a frequency range from 1 to 65 GHz. The network analyzer is calibrated using a two-port short/open/load/through method. On-wafer open and short structures is used to eliminate the effects of parasitic elements. Figure 4a shows the current gain (|h₂₁|²), unilateral gain (U), and the maximum stable gain (MSG) as a function of frequency at V_ds = 10 V, V_gs = − 3 V after de-embedding. f_T/f_max of 140/215 GHz for the InAlN/GaN HEMT with a 50-nm gate length is obtained by extrapolation of |h₂₁|² with a − 20 dB/dec slope. An (f_T × f_max)^1/2 of 173 GHz is obtained, which is the highest record value among the reported InAlN/GaN HEMTs on Si with regrowth-free ohmic contact technology. To the best of our knowledge, a high (f_T × f_max)^1/2 of 226 GHz (f_T/f_max = 250/204 GHz) was achieved on a 55-nm InAlN/GaN HEMT on Si⁵, and a high (f_T × f_max)^1/2 of 239 GHz (f_T/f_max = 190/300 GHz) was demonstrated on the e-mode high-k InAlN/GaN MISHEMTs with L_g of 50 nm¹⁰. The ohmic contact regrowth technology was used in both reported devices. Here for our device, the alloyed ohmic resistance (R_C: 0.3 Ω mm) is higher than the reported regrowth ohmic contact resistance (R_C: 0.05 Ω mm)⁵. This presents a high potential for the RF performance improvement by further decreasing the ohmic contact resistance. Due to f_T/f_max of 140/215 GHz, products of f_T × L_g and f_max × L_g of 7.0 and 10.75 GHz·µm are achieved, respectively. Although neither passivation nor field plate technology is used, the 140-GHz InAlN/GaN HEMT with an BV_ds of 36 V presents a Johnson’s figure-of-merit (JFOM = f_T × BV_ds) of 5.04 THz·V. Figure 4b shows the measured f_T and f_max of the 50-nm InAlN/GaN HEMT as a function of V_gs. Both f_T and f_max show a gradual decrease compared with their peak values, presenting a good device linearity.

Figure 4

(a) RF performance of the InAlN/GaN HEMT with a 50-nm gate length at V_gs = − 3 V and V_ds = 10 V with f_T/f_max = 140/215 GHz. (b) The f_T and f_max as a function of V_gs.

Equivalent circuit model

The classical 16-element equivalent-circuit model is used for the InAlN/GaN HEMT, as shown in Fig. 5a^23,24. Based on this model, the device extrinsic and intrinsic parameters are extracted in Table 1^23,24,25. The slight discrepancy between the simulated and measured S-parameter values is observed in Fig. 5b, verifying the accuracy of the extracted extrinsic and intrinsic parameters. The f_T and f_max can be calculated using^23,26

$$\begin{aligned} f_{T} & = \frac{{G_{m} /G_{0} }}{{2\pi ((C_{gs} + C_{gd} )(1/G_{0} + (R_{s} + R_{d} )) + (C_{gd} \cdot G_{m} /g_{0} )(R_{s} + R_{d} ))}}, \\ f_{\max } & = \frac{{f_{T} }}{{2\sqrt {(R_{s} + R_{g} + R_{i} ) \cdot G_{0} + 2\pi f_{T} R_{g} C_{gd} } }}. \\ \end{aligned}$$

(1)

where G_m and G₀ are the intrinsic transconductance and drain-source conductance, respectively; C_gs and C_gd are the gate-source and gate-drain parasitic capacitance, respectively; R_s, R_d, R_g, and R_i are the parasitic source access resistance, drain access resistance, gate electrode resistance, and input resistance, respectively.

Figure 5

(a) Equivalent-circuit model for InAlN/GaN HEMT. The intrinsic elements are shown in the red dashed box. (b) Comparison of the simulated and measured S-parameters for the InAlN/GaN HEMT with a 50-nm gate length at V_ds = 10 V and V_gs = − 3 V.

Table 1 The extracted extrinsic and intrinsic parameters for the 50-nm InAlN/GaN HEMTs.

The calculated f_T/f_max = 145/218 GHz is very close to the value (f_T/f_max = 140/215 GHz) extracted by the extrapolation of |h₂₁|² with a − 20 dB/dec slope, which confirms the excellent RF performance. The high intrinsic transconductance/drain-source conductance (G_m/G₀) ratio of 10.6 contributes to the high f_max.

Scaling behavior

The InAlN/GaN HEMTs with L_g between 50 and 350 nm are fabricated. Figure 6a shows the measured f_T/f_max of the InAlN/GaN HEMTs with different L_g at V_gs = − 3 V and V_ds = 10 V. The devices with L_g of 50, 70, 100, 150, 250, and 350 nm present f_T/f_max of 140/215, 135/205, 120/170, 90/160, 60/136, 36/128 GHz, respectively. f_T × L_g and f_max × L_g are obtained in Fig. 6b. A f_T × L_g peak of 15 GHz µm is achieved on the 250-nm-gate-length InAlN/GaN HEMT with a f_T of 135 GHz. f_max × L_g presents a decrease from 44.8 GHz µm (L_g = 350 nm) to 10.75 GHz µm (L_g = 50 nm). The decrease of both f_T × L_g and f_max × L_g as L_g scales down means that the effect of parasitic parameters is more pronounced, thus hindering the improvement of f_T and f_max. Due to the large head length of T-shaped gate (L_head = 400 nm), the transistors features higher f_max and f_max × L_g.

Figure 6

(a) Measured f_T and f_max as a function of L_g at V_gs = − 3 V and V_ds = 10 V. (b) f_T × L_g and f_max × L_g as a function of L_g.

To shed more light on the scaling behavior, the extrinsic and intrinsic parameters of these devices are further extracted using the equivalent circuit model discussed above. C_gs can be separated to two parts: gate-source intrinsic capacitance (C_gs,int) and gate-source extrinsic capacitance (C_{gs, ext}). It means C_gs = C_gs,int + C_gs,ext²⁷. C_gd can also be written as C_gd = C_gd,int + C_gd,ext. Figure 7 shows the extracted C_gs and C_gd as a function of L_g. Both C_gs and C_gd present a linear dependence upon L_g. By linear fitting, the C_gs,ext and C_{gd, ext} are obtained from C_gs and C_gd at L_g = 0 nm²⁷, as shown in Fig. 7. Here C_gs,ext of 93.05 fF/mm and C_gd,ext of 97.65 fF/mm are determined, respectively.

Figure 7

Measured and linear fitted (a) gate-source parasitic capacitance C_gs and (b) gate-drain parasitic capacitance C_gd as a function of L_g at V_gs = − 3 V and V_ds = 10 V.

The total delay (τ) of transistors can be written as^27,28

$$\tau = \frac{{1}}{{{2}\pi f_{T} }} = \tau_{t} + \tau_{ext} + \tau_{par}$$

(2)

Here τ is partitioned into three components: transit time (τ_t), parasitic charging delay (τ_ext), and parasitic resistance delay (τ_par).

τ_t is the transit time under the gate region. It is related to the gate length as well as the electron velocity (v_e) under the gate region, and can be calculated by^27,28

$$\tau_{t} = \frac{{C_{gsi} + C_{gdi} }}{{G_{m} }} = \frac{{L_{g} }}{{v_{e} }}$$

(3)

τ_ext is parasitic charging delay through C_gs,ext as well as C_gd,ext, and can be written as^27,28

$$\tau_{ext} = \frac{{C_{gs,ext} + C_{gd,ext} }}{{G_{m} }}.$$

(4)

τ_par is parasitic resistance delay mainly associated with R_s as well as R_d, and can be written as^27,28

$$\tau_{par} = C_{gd} (R_{s} + R_{d} )\left[ {1 + \left( {1 + \frac{{C_{gs} }}{{C_{gd} }}} \right)\frac{{G_{0} }}{{G_{m} }}} \right].$$

(5)

Figure 8 plots τ_t and v_e as a function of L_g calculated from (3). As L_g decreases, τ shows a monotonous drop, which corresponds to the increased f_T. With decreased L_g, v_e increases to a maximum value of 1.08 × 10⁷ cm/s (at L_g = 150 nm) and then drop to 0.80 × 10⁷ cm/s (at L_g = 50 nm). Figure 9 shows the extracted G_m and G₀ from the equivalent-circuit model as a function of L_g. G₀ shows an increase with decreased L_g. The dependence of G_m and v_e on L_g present the same trend. Based on (3), because C_gsi and C_gdi linearly depends on L_g, we conclude that the change of G_m is attributed to v_e difference. The same trend of G_m and v_e on L_g is also observed in InAs HEMTs and result from the short channel effect^29,30,31.

Figure 8

Extracted transit time (τ_t) and electron velocity (v_e) as a function of L_g at V_gs = − 3 V and V_ds = 10 V.

Figure 9

Extracted intrinsic transconductance (G_m) and intrinsic conductance (G₀) as a function of L_g at V_gs = − 3 V and V_ds = 10 V.

Figure 10 exhibits the calculated τ_t, τ_ext, and τ_par using (3)–(5). τ_ext and τ_par is almost unchanged. Conversely, τ_t decreases with decreased L_g and dominates the total delay in all devices. This makes it possible to decrease delay and improve f_T through downscaling of device gate length. However, for the device with L_g below 100 nm, the effect of τ_ext and τ_par become non-negligible. The ratios of (τ_ext + τ_par)/τ_t are 39% and 40% for the InAlN/GaN HEMTs with L_g of 70 and 50 nm, respectively. This means the parasitic capacitance and resistance significantly hampers further L_g scaling benefits in RF performance of sub-100 nm InAlN/GaN HEMTs.

Figure 10

Extracted delay components as a function of L_g. The delay (τ) is partitioned into three components: transit time (τ_t), parasitic charging delay (τ_ext), and parasitic resistance delay (τ_par).

Therefore, downscaling and decreasing parasitic resistances as well as capacitances are very important for further improving device performance of InAlN/GaN HEMTs on Si. Figure 11 plots the calculated f_T and f_max based on the model and the extracted parameters (Blue-line in Fig. 11), which shows a good agreement with the measured results. In terms of the electron velocity saturation, the electron velocity of the InAlN/GaN HEMTs with L_g < 50 nm is assumed to be the same as that with L_g = 50 nm. With the obtained v_e, τ_t can be obtained using (3), τ_ext is parasitic charging delay through C_gs,ext and C_gd,ext, and both are the constant as shown in Fig. 7. τ_par is mainly associated with R_s and R_d, which are independent on L_g. As shown in Fig. 10, τ_ext and τ_par present slight change with L_g. So here τ_par of the device with L_g = 50 nm is used during the model calculation. Then f_T can be calculated with the obtained τ_t, τ_ext and τ_par by using (2). When L_g decrases from the 50–20 nm, the T-shaped gate head length of 400 nm is unchanged, so the effect of the small gate length variation on R_g and R_i is miminal. Hence R_g and R_i of device with L_g of 50 nm are used. C_gd is extracted from the linear fitting in Fig. 7b and then f_max is obtained using (1). The model results present that f_T/f_max of 230/327 GHz can be achieved when L_g scales down to 20 nm with the technology developed in the study. To decrease the parasitic resistance, the regrowth ohmic contact can be used. Here R_s (0.30 Ω mm), R_d (0.32 Ω mm), and G_m (573 mS/mm) are changed to 0.10 Ω mm, 0.08 Ω mm, and 620 mS/mm⁵. Then new model results with regrowth technology are plotted (Green-line in Fig. 11) and a f_T/f_max of 265/397 GHz is achieved on the device with a 20-nm gate length. Optimizing the detailed structure of T-shaped gate can decrease C_gs and C_gd. Hence when 30% decreasing of C_gs and C_gd is added into the model, new results (Red-line in Fig. 11) are plotted and an improved f_T/f_max of 320/535 GHz on 20-nm-gate-length InAlN/GaN HEMT is demonstrated. These values are comparable to the 27-nm InAlN/GaN HEMTs on SiC with f_T/f_max of 348/340 GHz, suggesting the possibility of further improvement of InAlN/GaN HEMTs on Si.

Figure 11

f_T and f_max under measured results (Scatters), obtained from model with extracted parameters (Blue-line), model with regrowth ohmic contact(Green-line), and model with regrowth and 30% decreased C_gs and C_gd (Red-line).

Conclusions

In summary, high-performance 50-nm InAlN/GaN HEMT on Si with an I_on/I_off ratio of 7.28 × 10⁶, a SS of 72 mV/dec, a DIBL of 88 mV/V, a BV_ds of 36, a f_T/f_max of 140/215 GHz, and a JFOM of 5.04 THz V are demonstrated. The extrinsic and intrinsic parameters of transistors with different L_g are extracted and the scaling behavior of InAlN/GaN HEMTs on Si is demonstrated. Based on extracted model, a f_T/f_max of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrowth ohmic contact technology and 30% decreased parasitic capacitance. This study confirmes the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.