Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs

Two-dimensional semiconducting materials of the transition-metal-dichalcogenide family, such as MoS2 and WSe2, have been intensively investigated in the past few years, and are considered as viable candidates for next-generation electronic devices. In this paper, for the first time, we study scaling trends and evaluate the performances of polarity-controllable devices realized with undoped mono- and bi-layer 2D materials. Using ballistic self-consistent quantum simulations, it is shown that, with the suitable channel material, such polarity-controllable technology can scale down to 5 nm gate lengths, while showing performances comparable to the ones of unipolar, physically-doped 2D electronic devices.

Scientific RepoRts | 7:45556 | DOI: 10.1038/srep45556 is eliminated, and the Schottky barriers created at the source and drain contact are tuned by an additional gate, namely program gate (PG), in order to select the charge carriers that can be injected in the channel. This class of devices allows the dynamic selection of the transistor polarity by the use of the PG, acting at the contact interfaces, while the control gate (CG), placed in the central region of the channel, controls the ON/OFF status of the device, as measured in Fig. 1(b,c).
The possibility of using electrostatic doping to control the device polarity avoids any complicated doping step during the fabrication process, to the benefit of fabrication simplicity and device regularity. In fact, no separate fabrication process is needed for n-or p-type devices, as the polarity can be dynamically controlled at runtime by the PG. Moreover, the device switching properties become more expressive, as each device is now acting as a comparison-driven switch and will allow the realization of compact logic gates, thus improving the computational density in 2D-flatronics 23,24 . However, to date, scaling opportunities with 2D materials have been theoretically explored only in unipolar, physically-doped devices, with Ohmic contacts [11][12][13][14]25 . This has been done disregarding the great difficulties that the accurate and controlled doping of the material brings to the fabrication  process, i.e., doping is already one of the major sources of variability in silicon CMOS devices 26 , and that achieving Ohmic contact to 2D materials has, so far, proven to be a challenging task. Here we study, for the first time, scaling opportunities for polarity-controllable devices based on 2D materials of the TMDCs family. To estimate the electrical characteristics of such ultra-scaled devices, we use ballistic self-consistent quantum simulations in the non-equilibrium Green's function (NEGF) formalism, as described in Methods. We first explore scaling for devices based on WSe 2 , the most promising material for which experimental results, presented in Fig. 1, are available 23 , and then focus on the selection of novel 2D semiconductor, for which experimental demonstrations are still lacking, to enhance the performances of the device. We show that such device can achieve performances that are comparable to unipolar doped devices with Ohmic contacts simulated with a similar approach, while bringing considerable simplifications to the fabrication process and bearing the promise of enhanced performances at circuit level. Figure 2 shows the 3D schematic structures of the simulated devices with top-gate (TG) and double-gate (DG) geometry ( Fig. 2(a,b), respectively). In the top-gate configuration, HfO 2 (κ = 25, equivalent oxide thickness (EOT) = 0.47 nm) was used as top dielectric, while SiO 2 (κ = 3.9, EOT = 30 nm) was considered as bottom dielectric. For the double-gate geometry HfO 2 (κ = 25, EOT = 0.47 nm) was used for top and bottom gate dielectrics. We modeled the 2D semiconducting channel with a 2-band tight-binding (TB) Hamiltonian, created from the material properties shown in Table 1 (see also Methods).

Methodology
The model was extended to bilayer 2D materials by adding an interlayer hopping parameter in the effective-mass Hamiltonian, to account for coupling between the two layers 27 . We studied the device switching properties performing self-consistent ballistic simulations, iteratively solving Poisson and Schrödinger equation (within the NEGF formalism), with an open-source quantum transport code 28,29 . No doping was introduced at source and drain contacts for both gate geometries and we assumed mid-gap SB contacts, to have symmetric characteristics for the two polarities. We evaluated the device performances at different gate lengths, keeping the same length for both the CG and PG gates (L CG = L PG ) and fixing the length of the ungated channel region  p-type operation for V PG = − 1 V. In this case, the negative voltage applied to the PG enables holes (h + ) to be injected in the channel at source (green arrow). In a similar way, as described for n-type operation, the potential barrier created by the CG blocks the flow of holes from source to drain (red crossed line).
Scientific RepoRts | 7:45556 | DOI: 10.1038/srep45556 (L OPEN ), separating PG and CG, to L CG /2, as shown in Fig. 2. Thus, in the remainder of the article, we will refer to L G as the length of each gated segment. The program gates are placed in close proximity to source and drain contact (an underlap of 0 nm is used in all simulations) in order to provide the most efficient modulation of the Schottky barrier. For each simulated transfer characteristic, the value of the voltage applied to the program gate (V PG ) was fixed, thus setting the device polarity, and the switching properties as a function of the control gate voltage (V CG ) were studied.

Results and Discussion
The operation principle of the device is shown in Fig. 3 with the help of the band-diagrams extracted from the simulations on monolayer (1 L) WSe 2 at L G = 8 nm. The PG controls the device polarity by tuning the effective Schottky barriers height (φ SB ) at source and drain (n-type behavior at V PG = 1 V in Fig. 3a and p-type behavior at Fig. 3b) while the control gate (CG) determines the ON/OFF state of the FET by controlling the potential barrier in the central region of the channel. Our simulation results show that the polarity of the device can be controlled at ultra-scaled dimensions, down to 4 nm gate lengths, when direct tunneling through the CG potential barrier begins to considerably degrade the device OFF-state. Figure 4 shows the simulated p-and n-type transfer characteristics for 1L-WSe 2 channel, with TG ( Fig. 4(a,b)) and DG (Fig. 4(c,d)) geometry. The gate length is varied to show the impact of scaling on the device characteristics. It is found that 1L-WSe 2 provides excellent control of the device OFF-state, thanks to the high bandgap (~1.5 eV) 30 , but also severely limits the ON-current of the device due to the high Schottky barrier (φ SB = 0.75 eV) present at source, where carriers are injected in the channel. The modulation induced by the PG at ± 1 V is enough to show conduction of charge carriers, but the ON-currents only reach values of a few μ A/μ m for DG geometry.
Therefore, to increase the ON current of the devices, bilayer (2 L) WSe 2 was studied as a channel material. In its bilayer form WSe 2 shows a reduced bandgap of ~1.1 eV 31 , which together with the increased mobile charge density, provided by the additional layer, is predicted to improve the device ON-state. Figure 5 shows the simulated transfer characteristics of 2L-WSe 2 FETs for both polarities and gate geometries, at different gate lengths.
As a result of the decrease in Schottky-barrier height at the contact interface (φ SB = 0.55 eV), the ON-currents are increased by 2 orders of magnitude. With the lowering of the semiconducting bandgap, the potential barrier created by the CG in the OFF-state of the device is also decreased, deteriorating the device OFF-current. The I OFF is increased by almost 3 orders of magnitude. Nevertheless, the transfer characteristics presented in Fig. 5, show that even at the shortest gate length simulated (L G = 4 nm), I OFF is still on the range of 10 −4 μ A/μ m, providing I ON /I OFF > 10 6 . The use of a DG geometry benefits the electrostatic control of the gates over the channel, and eliminates the charge screening effect between the layers that occurs in the TG structure. The improvement in the device electrostatics, given by the DG configuration, is shown in Fig. 6 where the I OFF and I ON (Fig. 6(a,b) respectively), extracted from the transfer characteristics of n-type devices with TG and DG structures, are compared. It is found that, until L G = 5 nm, the OFF-current in the DG configuration is consistently 1 order of magnitude lower with respect to the TG geometry, while the ON-current shows an average 2× improvement. For L G = 4 nm, the potential barrier created by the CG starts to become thin enough to have tunneling effects, deteriorating the OFF-state of the device and thus lowering the positive impact of the double-gate. Similar results can be found for the p-type characteristics simulated on the same device.
Further analysis is presented in Fig. 7, where the effect of scaling on the sub-threshold slope (SS) and on the drain-induced barrier lowering (DIBL) is analysed. The SS is evaluated as the average slope of the transfer characteristics in the sub-threshold regime (from − 0.2 to 0.2 V CG ) for both p-and n-type operation mode ( Fig. 7(a,b) respectively). For both polarities, it is shown that the SS greatly benefits from the double-gate geometry, which is able to mitigate the detrimental effect of increased channel thickness for the bilayer device. The DIBL is calculated as the variation of threshold voltage (V th ) of the device divided by the variation of applied V DS (DIBL = Δ V th /Δ V DS ) and is expressed in mV/V. A threshold voltage shift of ~25 mV can be estimated as the lateral shift, at the end of the subthreshold regime, between the transfer characteristic simulated at V DS = 0.1 V and 0.6 V (see Fig. 7c). Thus we computed a DIBL of 50 mV/V for L G = 6 nm, showing excellent immunity to DIBL effects. The observed immunity to DIBL is an added benefit of the SB polarity-controllable FETs, as the drain voltage drop in the channel is concentrated at the Schottky junction at drain. The change in V DS does not affect the height of the potential barrier created by the CG, which is ultimately responsible for the lowering of the threshold voltage of the device.
These analyses showed that the double-gate geometry provides the best electrostatic control and enhances the performances of the device by lowering the I OFF , while improving the I ON and SS. Nevertheless, the I ON reachable with 2L-WSe 2 , in both n-and p-type operation mode, are still too low to provide a successful scaling path with this material. The Schottky barriers at source and drain (φ SB = 0.55 eV) are too high to have efficient tunneling at the contact interface. However, theoretical calculations [32][33][34] have shown that in the family of 2D-TMDCs, several materials, such as ZrS 2 , HfS 2 , HfSe 2 , etc., have a lower semiconducting band-gap (0.7-0.9 eV) and could prove to be well suited for application in SB-DIG FETs. For many of these materials experimental evidences are still absent or very limited [35][36][37][38][39] , and even in the theoretical ab-initio calculations there are discrepancies in the computed material properties [32][33][34] (with great variations especially in the value of the semiconducting band-gap, depending of the functional used in ab-initio simulations). Based on these theoretical analyses, we modeled a 2D-material, according to the properties presented in Table 1, and studied its potential application as a semiconducting channel in polarity-controllable FETs. We considered a 2L-MX 2 material with an increased lattice constant, a lower bandgap and similar effective masses with respect to WSe 2 (as it is predicted for ZrS 2 , HfS 2 , HfSe 2 ). Figure 8(a,b) shows the transfer characteristics at different L G for a DG geometry for both p-and n-type polarities, while the device performances in terms of I ON /I OFF ratios are presented in Fig. 8c. The lower Schottky-barrier height at source and drain (φ SB = 0.4 eV) allow for a greater number of carriers to be injected in the channel, increasing the I ON to ~1.5 mA/μ m, while keeping I OFF well below 10 −2 μ A/μ m down to L G = 5 nm. The lower I ON /I OFF ratios for n-type behaviour shown in Fig. 8c, are caused by the lower effective mass of electrons, which increases the transmission probability of carriers over the potential barrier created by the CG, thus increasing the I OFF .

Conclusions
We evaluated scaling trends and device performances for 2D polarity-controllable FETs using self-consistent ballistic quantum-transport simulations. The device concept presents the great advantage of using only a single 2D channel material for both device polarities and does not require complex doping techniques. We showed the feasibility of controllable-polarity behaviour at the nanoscale level thanks to the additional program gate  introduced in the device geometry. We first simulated the performances of mono-and bi-layer WSe 2 , as a channel material, and found that the high semiconducting band-gap (~1.5 eV and 1.1 eV respectively) prevents achieving high ON-currents. Thus we studied the benefits of bilayer-MX 2 materials, such as ZrSe 2 , HfS 2 , or HfSe 2 , for which ab-initio simulations have shown the presence of a lower semiconducting bandgap (0.7-0.9 eV). Due to the lack of experimental characterization and the disagreement between different ab-initio simulations, we modeled a bilayer-MX 2 with electrical properties (effective masses and bandgap) within the values reported in literature [32][33][34] . For the simulated MX 2 material, we showed I ON > 10 3 μ A/μ m and I ON /I OFF > 10 5 down to L G = 5 nm for both pand n-type polarities. These performances are comparable with the ones predicted, using ballistic self-consistent transport simulations 7,8 , for conventional doped devices based on 2D-TMDCs, and thus show a feasible scaling path for 2-dimensional polarity-controllable devices for beyond-CMOS flatronics.

Methods
Material properties and Device simulations. To perform quantum simulations within NEGF formalism, we use a 2-band tight-binding Hamiltonian to model the conduction and valence band of a chosen material 40 . We calculated the hopping parameter t hop , to be used by the NanoTCAD ViDES 28,29 in the NEGF simulations, as 40 : where a is the lattice constant, E G is the energy band-gap, ⁎ m R is the reduced effective mass and ħ is the reduced Plank constant. Here, the material parameters such as lattice constant, effective masses and band-gaps are taken from literature [30][31][32][33][34] and reported in Table 1. This approach has been widely used to project performance of nanoscale transistors based on Si, III-V 41 and now 2D materials [11][12][13][14] . Further, to model Schottky contacts, we extend our Hamiltonian at the contacts for the zero-bandgap metal and applied Dirichlet boundary conditions. This model provides a good trade-off between accuracy and computational time which is crucial in advanced device design with exotic materials for future technology nodes.