Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications

Complementary power field effect transistors (FETs) based on wide bandgap materials not only provide high-voltage switching capability with the reduction of on-resistance and switching losses, but also enable a smart inverter system by the dramatic simplification of external circuits. However, p-channel power FETs with equivalent performance to those of n-channel FETs are not obtained in any wide bandgap material other than diamond. Here we show that a breakdown voltage of more than 1600 V has been obtained in a diamond metal-oxide-semiconductor (MOS) FET with a p-channel based on a two-dimensional hole gas (2DHG). Atomic layer deposited (ALD) Al2O3 induces the 2DHG ubiquitously on a hydrogen-terminated (C-H) diamond surface and also acts as both gate insulator and passivation layer. The high voltage performance is equivalent to that of state-of-the-art SiC planar n-channel FETs and AlGaN/GaN FETs. The drain current density in the on-state is also comparable to that of these two FETs with similar device size and VB.

Scientific RepoRts | 7:42368 | DOI: 10.1038/srep42368 oxygen point defects O i 15,16 or the aluminium vacancies V AL 15 . These levels are located below the C-H diamond valence band edge, as shown in Fig. 2a. The Oi level (unoccupied states) is located 1.0 eV 16 above the valence band edge and the valence band offsets between C-H diamond and Al 2 O 3 are 2.9 eV 17 and 3.9 eV 18 , respectively. When the Oi states near the interface are occupied by electrons with a density of more than 10 12 cm −2 , 2DHG formation with an equivalent hole density near the interface in C-H diamond satisfies the charge neutrality condition.
Using the high temperature (450 °C) ALD Al 2 O 3 as gate oxide and passivation of gate-drain region (drift region), a C-H diamond metal oxide semiconductor (MOS) FET was uniquely designed for high-voltage and high-temperature operation. It is shown schematically as a cross-sectional structure in Fig. 2b and as a 3D image in Fig. 2c. The MOSFET shows clear pinch-off and saturation characteristics with a high on-off ratio in the temperature range from − 263 °C (10 K) to 400 °C (673 K) (Supplementary Figs S2 and S3).
We consider two typical MOSFETs, which both have Al 2 O 3 gates; the first has a passivation oxide thickness of 200 nm, a gate length (L G ) of 2 μ m, a source-gate distance (L SG ) of 2 μ m and a gate-drain distance (L GD ) of 17 μ m, while the second has an oxide thickness of 400 nm, an L G of 9 μ m, an L SG of 3 μ m and an L GD of 16 μ m, and their maximum drain current densities (I DS ) were 116 mA/mm and 110 mA/mm, according to their I DS -V DS characteristics ( Fig. 3a and c), respectively. The two MOSFETs exhibited breakdown voltages (V B ) of 1538 V and 1662 V (Fig. 4a, Fig. 5), respectively. Using a device simulation based on the two-dimensional negatively charged sheet model (Fig. 2a, Fig. 6a, Supplementary Fig. S4), the I DS -V DS characteristics shown in Fig. 3a were reproduced almost exactly in terms of their V GS dependence in Fig. 3b using a negative charge areal density (N S ) of 5 × 10 12 e cm −2 with a hole channel mobility of 80 cm 2 V −1 s −1 at the Al 2 O 3 /C-H diamond interface. In general, the charge sheet model is successful in reproducing the characteristics of an AlGaN/GaN FET, where the interface polarization produces the positive charge sheet that is responsible for the two-dimensional electron gas. At the Al 2 O 3 /C-H diamond interface, a 2DHG might be formed by the negatively charged sites near the interface as shown in Fig. 2a.
The off-state characteristics before breakdown of the diamond MOSFETs of Al 2 O 3 (mostly 200 nm in thickness) with a common gate width (25 μ m) and different gate-drain length (L GD ) values of 9, 16, 17, and 22 μ m were investigated at room temperature (RT) and at higher temperatures until breakdown started to occur, and the results are shown in Fig. 4. V GS for the off-states are + 20-+ 60 V. The maximum V B at each L GD are 996 V (L GD = 9 μ m), 1270 V (20 μ m, 300 °C), 1512 V (17 μ m, 200 °C), 1646 V (22 μ m), and 1662 V (16 μ m, with a thicker oxide layer of 400 nm). The source-drain current (drain leakage current) I DS gradually increases at higher temperatures. At 800 V, the leakage currents at room temperature range from 2 × 10 −7 to 5 × 10 −6 A/mm (Fig. 4a) and the corresponding values at 200 and 300 °C are 8 × 10 −6 A/mm and 10 −3 A/mm (Fig. 4b), respectively. In general, the drain leakage current increases gradually at a high voltage (high electric field) and breakdown starts to occur. These values are acceptable for power device applications. In contrast, the source-gate-drain current (or gate leakage current) I DGS is one to two orders of magnitude less than I DS , as shown in Fig. 4. At the start of the breakdown process, when I DGS reaches I DS , gate-drain breakdown through the gate oxide may be a main cause. One such example is a FET with L GD = 9 μ m and V B = 996 V (see Fig. 4a). In other cases, however, I DGS is less than I DS by more than an order of magnitude at breakdown. Most breakdown processes are initiated at the drift region near the gate. This is an almost ideal circuit and is much simpler than that used in current inverter circuits, in which n-channel FETs are used in both the upper and lower arms, and the source potential in the upper arm is not fixed and thus must be changed by on-off switching. An extra gate drive circuit is needed in the current inverter circuit to apply the appropriate gatesource voltage, but is not required in the complementary system shown.
Scientific RepoRts | 7:42368 | DOI: 10.1038/srep42368 The maximum breakdown voltage V B at each L GD is shown in Fig. 5 with two different passivation thicknesses (200 nm and 400 nm). When L GD is 1 μ m, V B = 365 V is obtained ( Supplementary Fig. S5). For a short L GD of 1 μ m, the punch-through condition (under which the difference between the electric fields along the Al 2 O 3 /C-H diamond interface on the gate and drain sides is small) has been applied based on the electric field distribution that can be calculated via device simulations, as discussed later in this work. The averaged electric field is simply calculated to be V B /L GD = 3.6 MV/cm. This value is equivalent to that of the breakdown fields of SiC and GaN. As L GD increases to 9 μ m, V B also increases and reaches 996 V at L GD = 9μ m. As L GD increases further, V B also increases correspondingly until L GD = 22 μ m. V B values of 1600 V and 1646 V are obtained at L GD = 20 and 22 μ m (Fig. 5), respectively. With a thicker (400 nm) Al 2 O 3 passivation layer between the gate and the drain, V B values from 1097 to 1708 V are obtained from L GD = 11 to 16 μ m (Fig. 5). When a thicker oxide layer is used, V B increases above 1000 V up to 1700 V with increasing L GD . The peak electric field at diamond side with thicker passivation layer (400 nm) is decreased by 25-30% compared with that of 200 nm thickness (discussed later). The V B of 1708 V ( Supplementary Fig. S6) is the highest value ever reported for a diamond FET with on-state I DS ~100 mA/ mm, and is comparable to that of SiC 19 or AlGaN/GaN 20,21 FETs with similar L GD (Table 1).
In the off-state of the MOSFET with the two-dimensional negative charge sheet (Fig. 2a, Fig. 6a), the electric field along the Al 2 O 3 /C-H diamond interface in the lateral direction contains a peak that occurs near the gate edge, as indicated by the cross shown in Fig. 2b, with a maximum value denoted by E M . The electric field along the Al 2 O 3 /diamond interface decreases with increasing distance from the gate edge, and almost reaches zero at a distance L 0 from the gate edge. The electric field distribution along the Al 2 O 3 /diamond interface is evaluated using MOSFET device simulations with various densities (N S ) of the 2D negative charges (1 × 10 11 × 10 13 cm −2 ) that were distributed homogeneously at the Al 2 O 3 /C-H diamond interface (Fig. 6a). In Fig. 6b and c, along the Al 2 O 3 /diamond interface, several of the electric field distributions that are responsible for V DS = 1600 V are shown for various N S . The reason why V DS = 1600 V was selected as an example here is that it is approximately equal to the frequently observed value of the highest operating voltage that is available in FETs at present. The V GS for the off-state is maintained at 30 V, so the gate-drain voltage drop is higher than the source-drain voltage drop. However, the gate potential does not have a major effect on the electric field or the potential distribution between the source and the drain. E M is effectively reduced by the thicker Al 2 O 3 (400-nm-thick) layer at each N S . At N S = 5 × 10 12 cm −2 , which reproduces an experimental I DS -V DS characteristic in the on-state ( Fig. 3a and b), the E M and L 0 values with the 200-nm-thick Al 2 O 3 layer are calculated to be 8.1 MV/cm and 3.5 μ m at V DS = 1600 V (Fig. 6b), respectively. The corresponding values when using a 400-nm-thick Al 2 O 3 layer are calculated to be 5.9 MV/cm and 4.5 μ m at 1600 V, respectively (Fig. 6c). Because the voltage drop of 1600 V occurs within the calculated L 0 (< 5 μ m), MOSFETs with V B ~1600 V are expected to be realized at an L GD of just over 5 μ m, but are actually obtained experimentally at L GD > 16 μ m (Fig. 5). This inconsistent result indicates that that the real value of L 0 is greater and the real E M is smaller than the values calculated based on N S = 5 × 10 12 cm −2 . It is reasonable that the effective value of N S is much lower than 5 × 10 12 cm −2 . At N S = 3 × 10 11 cm −2 , L 0 reaches 16 μ m, as shown in Fig. 6b and c. The fact that V B ~1600 V is obtained at an L GD of more than 16 μ m indicates that N S < 3 × 10 11 cm −2 . As shown in Fig. 5, the maximum value of V B is roughly proportional to L GD . This behaviour may also be caused by a lower effective charge density, such as N S < 3 × 10 11 cm −2 .
The original negative charge density can be either reduced or cancelled in one of two main ways. The first involves hole injection into the Al 2 O 3 layer on an undoped diamond layer. Energetic (hot) holes that are accelerated by a high electric field can enter the Al 2 O 3 layer beyond the large band offset between the Al 2 O 3 layer and C-H diamond (2.9-3.9 eV) (Fig. 2a) 17,18 . This effect on the electric field distribution can also be simulated using smaller N S values such as N S = 1 × 10 12 and 3 × 10 11 cm −2 , as shown in Fig. 6b and c. The other way involves use of positively ionized nitrogen donors in a nitrogen-doped diamond substrate (nitrogen concentration of 10 19 cm −3 ) under the undoped diamond layer (Fig. 2b). Substitutional nitrogen atoms that act as deep donors can be positively ionized via hole recombination with an electron from a neutral nitrogen donor. The deep donor level (1.7 eV) means that this positive charge can be maintained for a long time because of the very low density of the conduction electrons. The ionized donors are randomly distributed in a nitrogen-doped substrate beneath the undoped layer. For simplicity, we assume here that the donors are distributed as a positive charge sheet with a charge areal density of N B . In the device simulations, it is varied from 1-6 × 10 12 cm −2 at the bottom of the undoped diamond (Fig. 6a) and N S is fixed at 5 × 10 12 cm −2 (N S0 ), then N B compensates N S0 to produce N S0 − N B . When N S0 − N B produces values of 1 × 10 12 and 3 × 10 11 cm −2 , the corresponding electric field distributions (which are not shown here) are calculated to be almost the same as those shown at N S = 1 × 10 12 and 3 × 10 11 cm −2 in Fig. 6b and c. When N S0 − N B = 0, perfect charge compensation occurs and the electric field distribution becomes flat, as shown in Fig. 5b and c (indicated by the green lines). This is an ideal situation for high-voltage device structures such as super-junctions. When 1 × 10 12 cm −2 > N S0 − N B > − 1 × 10 12 cm −2 . the maximum I DS is preserved at 60-90% of the value obtained by the N S0 (Fig. 3b), indicating that the positively charged embedded layer does not reduce the channel and drift hole conduction so greatly near the surface. The drain current density (I DS ) of the diamond FET with the breakdown voltage of 1538 V and 1662 V exceeds 100 mA/mm, according to the I DS -V DS characteristics at low drain bias shown in Fig. 3. Saturation behaviour is observed at V GS > 0 V and pinch-off is obtained at V GS = 50 V. At V GS < 0 V, the drain current increases and becomes linear. Finally, the drain current does not increase further upon application of a more negative gate bias. The saturated slope of the I DS -V DS characteristic is mainly due to the gate-drain resistance, because it is the main resistive part of the high voltage device. However, the total drain on-current for a source-to-drain distance of 25-30 μ m is more than 100 mA/mm, which is comparable to the corresponding currents of SiC lateral MOSFETs  (90 mA/mm) 19 , AlGaN/GaN HFETs (300-600 mA/mm) 20,21 and AlGaN/AlGaN HFETs (200 mA/mm) 22 with an equivalent device size and V B (Table 1). A higher on-current can be achieved at a lower V DS by increasing either the hole areal density or the sub-surface mobility.
The maximum I DS was investigated as a function of temperature for diamond FETs with the C-H channel (2DHG) and with a boron-doped channel (Fig. 7). The I DS of the C-H channel only changes by approximately 40% from − 263 °C to 300 °C. In the C-H channel MOSFETs, which show V B of more than 1000 V, I DS is approximately 20 mA/mm at V DS = 10 V and approximately 100 mA/mm at V DS = 50 V at room temperature. At higher temperatures, I DS decreases slightly because of the reduction in hole mobility caused by phonon scattering. In contrast, the boron-doped channel FETs with a high V B of more than 600 V show a rapid increase in I DS by more than one order of magnitude over the range from room temperature to 200-300 °C. This is caused by the activation of boron as a relatively deep acceptor (0.37 eV), with doping levels of 5 × 10 15 and 1 × 10 17 cm −3 in the metal-semiconductor field-effect transistor (MESFET) 23 and the junction FET (JFET) 24,25 , respectively. The drain current densities of the 2DHG channel are more than two orders and one order of magnitude higher than those of the boron-doped channel at room temperature and in 200-300 °C range, respectively.
Junction FETs, including MESFETs, regulate their depletion layer fronts far away from their p-n or MES junctions to control their bulk p-type channel thicknesses. Therefore, the drain current controllability in these  FETs is low, but the current is stable because the channel carriers are not affected by the junction charge. Because a MOSFET can control surface band bending, the current response of its gate is efficient, but it is also sensitive to interface charge. The 2DHG that occurs at the Al 2 O 3 /C-H diamond interface may originate from the electric field (band bending) that is induced by the negative charges in Al 2 O 3 near the interface and the applied gate voltage. The drain current can be increased or reduced effectively, because the C-H surface has a very low surface state density when compared with that of the C-O surface that is normally used in MESFETs. High performance 2DHG diamond MOSFETs with submicron gate lengths have already obtained maximum current densities of 1.2-1.3 A/mm 5,26 , on-resistances of 4-6 Ωmm 5 , and transconductances of 200-480 mS/mm 5 . These values are comparable to those of AlGaN/GaN devices of the same size. In the long L GD diamond FETs that are used for high voltage applications, however, the drain current density and the transconductance become more than one order of magnitude lower because of the low mobility (70-100 cm 2 V −1 s −1 ) in the 2DHG drift layer. Mobility enhancement of the 2DHG layer by up to 500 cm 2 V −1 s −1 or the discovery of a shallow acceptor with an acceptor level that is lower than 0.2 eV will dramatically improve the specific on-resistance for high voltage applications.

Conclusions
By creation of a 2DHG using a high-temperature ALD Al 2 O 3 layer on a C-H bond diamond surface, the following p-channel MOSFET characteristics have been obtained.
1) Off-state. When L GD increases from 1 μ m to 22 μ m, V B increases up to roughly 1600 V in the off-state with the increasing L GD . The maximum breakdown voltage is 1700 V at room temperature, 1500 V at 200 °C and 1200 V at 300 °C and 400 °C.
2) On-state. In the high voltage FET with V B of 1600 V, the maximum current density in the on-state when normalized with respect to the channel width is 100 mA/mm and is nearly constant from − 200 °C (73 K) to 400 °C (673 K).
These high-voltage breakdown characteristics in the off-state and the drain current density per unit gate width in the on-state are comparable to those characteristics of lateral SiC and III-nitride FETs. Because the 2DHG at the C-H diamond surface is ubiquitous and was stably covered with ALD Al 2 O 3 , the above FET performance can easily be transferred to vertical power devices such as trench gate MOSFETs. These results demonstrates the potential for application of a diamond p channel FET as a smart power inverter using complementary power FETs (Fig.1).

Method
The C-H diamond MOSFET for high voltage and high temperature operation is shown schematically as a cross-sectional structure in Fig. 2b and as a 3D image in Fig. 2c. The MOSFET fabrication process without deterioration of the C-H bonds is briefly described in the following. The starting substrate is synthetic diamond (001), which was formed under high-pressure and high-temperature (HPHT) conditions. In this HPHT synthetic diamond, nitrogen atoms are incorporated as deep donors at a concentration of 10 19 cm −3 . On this substrate, a nominally undoped diamond layer is homoepitaxially grown by microwave plasma-assisted chemical vapour deposition to a thickness of 0.5 μ m (Supplementary Fig. S7a). Source and drain metal contacts are then formed by Au/Ti deposition (Supplementary Fig. S7b). Most of the surface area, except for the source and drain contacts, is then H-terminated by remote plasma treatment at 600 °C ( Supplementary Fig. S7c). During that time, TiC is formed to erode the diamond layer to a depth of a few nm and subsequently form a stable contact to the diamond. The H-terminations are replaced with O-terminations through a local oxidation process to form an isolated region, and thus an H-terminated channel remains between the source and drain (Supplementary Fig.S7d).