Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS2) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS2 and pentacene. The pentacene/MoS2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices.


Fabrication of pentacene/MoS2 p-n junction device
shows the device fabrication processes of pentacene/MoS2 p-n junction devices.
First, SiO2 (270 nm thick)/Si substrate was prepared and cleaned by acetone, isopropanol, and de-ionized (DI) water for 15 min each ( Fig. S1(a)). Then, we transferred MoS2 flakes from a bulk MoS2 crystal onto the substrate by a mechanical exfoliation method ( Fig. S1(b)). And we found suitable MoS2 flakes that could be used as a field effect transistor (FET) using an optical microscope. To make patterns, we spin-coated methyl methacrylate (MMA) (9% concentration in ethyl lactate) and polymethyl methacrylate (PMMA) (5% concentration in anisole) as electron resist at 4000 rpm and baked the sample at 180°C for 90 s on a hot plate. And we made patterns on the electron resist layer using an electron beam lithography system with a 30 kV exposure. After patterning, the devices were soaked in a methyl isobutyl ketone/isopropyl alcohol (1:3) solution during 1 min for pattern development (Fig. S1(c)). Next, Au (50 nm thick)/Ti (5 nm thick) was deposited as the source and drain electrodes using an electron beam evaporator (KVE-2004L, Korea Vacuum Tech) with a deposition rate of 0.5 Å /s at pressure of ~10 -7 torr ( Fig. S1(d)). After the lift-off process with acetone, the source and drain electrode patterns were completed ( Fig. S1(e)). Then, we spin-coated the PMMA on MoS2 devices and made patterns to make p-n junction devices by using the electron lithography system ( Fig. S1 (f)). PMMA coating prevents the unwanted effects that were caused by pentacene which had been deposited on MoS2 FET channel. Finally, the pentacene active film (60 nm thick) was deposited by a thermal evaporator (GVTE1000, GV-Tech) with a deposition rate of 0.5 Å /s at pressure of ~10 -6 torr ( Fig. S1(g)). Figure S1. Schematics of fabrication process of pentacene/MoS2 p-n junction devices.  Figure S2 shows the mobility versus temperature of a MoS2 FET. If a device shows a band-like transport, mobility will have a temperature dependence such that mobility increases as temperature decreases. But in our case, the mobility of MoS2 FET device decreased as temperature decreased, which does not support the band like transport. It is caused by insufficient carrier density of our device. Band like transport in MoS2 FET occurr beyond a certain carrier density. The carrier density (n) of our MoS2 FET device was estimated as ~1.63  10 12 /cm 2 even at a large gate voltage, VG = 40 V. This value is smaller than the reported value 3.6  10 12 /cm 2 that showed band-like transport. S1   Figure  Nt is the trap density in the channel, ε0 is the vacuum permittivity, εr is the dielectric constant, q is the elementary charge, and L is the channel length. S2 We could obtain the VC values at each gate voltage from Fig. S5. In VG = 0 V, only ID versus VD curves at below 175 K intersect each other, which can be due to property of MoS2 SCLC behavior. S3 In MoS2, at high temperature, the amount of free carrier density can be larger than the amount of trapped carriers. So, only ID versus VD curves at low temperature are appropriate in obtaining VC value.

Dimensional analysis of variable range hopping model in pentacene/MoS2
p-n junction device Figure S7 shows the VRH fittings of a pentacene/MoS2 p-n junction device in one (1D), two (2D), and three (3D) dimension. And Table S1 shows the value of the coefficient of determination (r 2 ) of the fittings at each gate voltage and dimension. Here, r 2 is a parameter that describes the quality of fittings and r 2 close to 1 indicates better quality of fitting. From Table S1, the fitting values of r 2 were the most closest to 1 at 3D fitting condition although the VRH fittings between dimensionalities were not significantly different.     Figure S8 shows the VRH fittings of control

Schoktty barrier model analysis of control MoS2 and pentacene FETs
Figure S10(a) shows IDSVDS curves of a MoS2 FET at various temperatures. We used the conventional thermionic emission equation for FETs data fitting to Schottky barrier model as In this equation, A is the Richardson constant, T is temperature, q is elementary charge, kB is Boltzmann constant, VDS is applied voltage to FET, and kB is effective Schottky barrier height.
Figure S10(b) shows the fitting result of MoS2 FET to Schottky barrier model from the data at VDS = 1 V. The high temperature data (T > ~175 K) was fitted well with Schottky barrier model (blue colored region in Figure S10(b)), whereas the low temperature data (T < ~ 175 K) wasn't fitted well with Schottky barrier model (red colored region in Figure S10(b)). At high temperature, carriers can be injected to FET by thermionic emission. However, at low temperature, effect of thermionic emission can be suppressed because of low thermal energy.
In the case of pentacene FET, Figure S10(c) shows IDSVDS curves at various temperatures.
And, Figure S10(d) shows the fitting result to Schottky barrier model from the data at VDS = 30 V. Similar to MoS2 FET case, high temperature data (T > ~175 K) was fitted well with Schottky barrier model (blue colored region in in Figure S10(b)), whereas the low temperature data (T < ~ 175 K) wasn't not fitted well (red colored region in Figure S10(b)).

Grains of pentacene on MoS2 flake and on SiO2
The atomic force microscopy (AFM) image of pentacene on a MoS2 flake and a SiO2 is shown in Fig. S11(a). And, the distribution of the grain size of pentacene on MoS2 and SiO2 is shown in Fig. S11(b) and S11(c), respectively. From these results, the average area of the grain size were extracted, which is summarized in Table S2. The results in Table S2 show that the grains of pentacene on MoS2 were smaller than those on SiO2. Smaller grain boundary could contribute to the trap site formation in the MoS2/pentacene p-n junction system.    Figure S12 shows the cross-sectional transmission electron microscopy (TEM) images of pentacene/SiO2 and pentacene/MoS2/SiO2. Uniformly deposited pentacene layer without visible defects was observed at the interface between the pentacene and SiO2 (Fig. S12(a)). However, relatively poor uniformity of the deposited pentacene layer was observed near the MoS2 flakes, as shown in Fig. S12(b) Defects near the MoS2 flakes (marked as the red circles in Fig. S12(b)) can act as the interfacial trap sites.