Physical Realization of a Supervised Learning System Built with Organic Memristive Synapses

Multiple modern applications of electronics call for inexpensive chips that can perform complex operations on natural data with limited energy. A vision for accomplishing this is implementing hardware neural networks, which fuse computation and memory, with low cost organic electronics. A challenge, however, is the implementation of synapses (analog memories) composed of such materials. In this work, we introduce robust, fastly programmable, nonvolatile organic memristive nanodevices based on electrografted redox complexes that implement synapses thanks to a wide range of accessible intermediate conductivity states. We demonstrate experimentally an elementary neural network, capable of learning functions, which combines four pairs of organic memristors as synapses and conventional electronics as neurons. Our architecture is highly resilient to issues caused by imperfect devices. It tolerates inter-device variability and an adaptable learning rule offers immunity against asymmetries in device switching. Highly compliant with conventional fabrication processes, the system can be extended to larger computing systems capable of complex cognitive tasks, as demonstrated in complementary simulations.

were not grafted and serve as reference. The AFM height profiles show the homogeneity of the films thickness along each electrode and between electrodes grafted separately.

III Supporting information for the memristive device a Discussion on device operating mechanism
The operating mechanisms of organic memristors are usually difficult to fully identify and there is little agreement in the literature on the filamentary vs. bulk nature of the switching and on the respective impact of the different elements (electrodes, organics, and substrates). In our case, the unipolar filamentary nature of the switching is clearly established based notably on the two following arguments: • Firstly, the device properties (threshold voltages and the maximum conductivity) do not scale with the junction area. As displayed in figure S5, devices with different junction area spanning a very large range display very similar characteristics. This implies that the change of conductivity only affects a small area rather than the entire junction.
• Secondly, as shown in figure 5d (main text), the RESET threshold varies with the initial conductivity, while the SET threshold does not. The higher the initial conductivity, the higher the voltage required to RESET the device. This can be explained if the organic memristor varies its conductivity through the formation and rupture of conductive filaments. It is indeed expected that when a larger conductive filament is formed, a higher energy is needed to break it.
Concerning the nature of the filaments, we excluded the role of the metal electrodes by changing the nature of one or both metals (including by using carbon nanotubes as electrodes). We also excluded the role of the surface (in planar junctions) notably by studying organic memristors on flexible organic substrates. Electrochemical characterizations show clear reversible memory effects in solution associated with redox process. Yet, in a device configuration, we cannot presently fully exclude the formation of carbon-based filaments originating from a degradation of the redox film during the electrical forming step. These elements will be presented separately in a publication specifically dedicated to the operating mechanism of electrografted organic memristors. The endurance of such vertical configuration is lower than for planar structures and the device failure is characterized by devices getting shorten. This is most probably due to partial deterioration of the organic layer upon metal evaporation. Work is underway on the electrografting parameters to improve the compactness of the film to limit such degradation.

IV Detail on Learning Algorithm
A binary version of WH is implemented to train the weight of a memristive device pair W i such that it maps input X i to output Y j . Weight change (∆) refers to a fixed change (α = 1) implemented at that case of the function in order to reduce error (difference between expected Y j and the actual line output V j ): Using this rule, n + 1 memristive pairs or 2n + 2 memristive devices are required to segregate n-input functions; each of the n + 1 inputs requires a negative and positive wire to separate states for that case, and negative and positive bias lines configure the entire line. Explicitly, a given input X i divides into two sign-symmetric input wires (X i+ , X i− ) that serve as input to two organic memristive devices M i+ , M i− , with conductances G i+ , G i− , respectively. A pair i produces synaptic weight W i as follows: where K is a normalizing factor. In response to a set of inputs X 1 · · · X n+1 , a shared post-synaptic potential X j is obtained automatically by linear combination of pair weights: X j is converted from current to voltage and subsequently from an analog to a digital value (sign(V j )) after it passes through a comparator set to ground. This has the effect of inverting the sign of X j . For every (2 n , where n is the number of bits ) case of the function's truth table, a common FSM checks whether the SNU's post-comparator output (O j ) is the same sign as expected (Y j ). If so, the next case is checked; else, if sign(Y j ) = sign(O j ), a programming pulse is sent.

VI Complete Demonstrator Learning Performance
7 linearly-separable 3-bit functions were attempted by our demonstrator using both programming styles (SO,SR). Of the 7 functions attempted, 5 were successfully learned in both cases. Success cases are highlighted below for both modes. Although a very small sample, mean values show that SR completes faster but 'wastes' many pulses in the process. Conversely, SO takes more epochs but less pulses. The former is explained by RESET overshoots; the latter, by 'sticky' devices that take many epochs to reach a high enough conductance.    figure 4f of the main text. It shows that RESET processes are dramatic in this case. It decrease the device conductivity to it minimum, while SET processes increase conductivity more gently. Figure S10. Simulated learning cases using SO (a) and SR (b) programming modes, with uniform nanodevices. 100% of all Monte Carlo iterations for every function learn successfully. Characteristic concluding conductances for one iteration for SO (c) are slightly higher than those for SR (d) since RESET is never used. In every SO case, for every device ∆G + = 10%G Max ; for every SR, ∆G + = ∆G − = 10%G Max . Legend for (c) and (d) is equivalent. Figure S11. Simulated learning cases using SO (a) and SR (b) learning with variable nanodevices (σ (G Max ) = 40%, σ (V t1 ) = σ (V t2 ) = 10%). Learning is imperfect and success varies slightly based on the function. Concluding conductances for a characteristic single iteration (c) are noticeably higher than those for a characteristic SR iteration (d). ∆G + , ∆G − vary on a device by device basis but always pegged at 10%G Max for the given device. learning of the first layer functions is nearly perfect, while the second layer function (3XOR) learns in 79.6% cases by mean 30.2 epochs. SO mode learning for the identical task is depicted in (b), (d) for first and second layers respectively. 71% of all cases now learn successfully, at a faster mean 23 epochs. Every simulation assumed device variability at the same levels examined in Figs. S10-S11; ∆G +,− = 10%G Max and the SR case is symmetric at this level. Figure S14. Classification performance as percentage of 10,000 Tests on the MNIST database answered correctly (guess g matches actual class value k) as a function of the number of examples chosen randomly from the pool of training examples (total 60,000) presented to obtain W (weight matrix of all memristive nanodevices). Blue and yellow lines use uniform devices (all have constant thresholds and maximum conductance). Green and orange lines introduce inter-device variability at σ = 10% around characteristic values µ(G Max ) = 60uS, µ(V t1 ) = 3V , µ(V t2 ) = 5.5V (for SO). In these cases, nanodevice conductance changes were set as ∆G + = 5%G Max , ∆G − = 5%G Max in SR, and ∆G + = 2.5%G Max in SO to prevent saturation of weights. Purple (uniform devices) and red (variable) series suggest the case in which every RESET is a violent one: that, is, ∆G + = 2.5%G Max , ∆G − = 5%G Max . Each point is the average of 5 simulations under different low starting conductances, in the uniform cases, and 10 simulations under different starting and dispersion values, in the variable cases. Figure S15. Classification performance (percentage of 10,000 tests answered correctly on the MNIST database) when 5,000 training samples are picked randomly from the training set and iteratively used to set W . Performance is given as the function of increasing dispersion parameter σ used to assign different threshold and maximum conductivity values to each of the simulated 15.6k organic memristive nanodevices for both SO, SR modes along a Gaussian spread. In every case, µ(G Max ) = 60µS, µ(V t1 ) = 3V , µ(V t2 ) = 5.5V (the last matters only for SR). For each simulation given as a point on the graph, 10 separate simulations were conducted and results averaged to reduce the effect of outliers. As before, ∆G + = 5%G Max , ∆G − = 5%G Max for SO, and ∆G + = 2.5%G Max .