Valley-engineered ultra-thin silicon for high-performance junctionless transistors

Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device.

temperature. Sub-band separation is a surface potential difference between two peaks when the derivative of conductance oscillation is zero. Since the surface potential could be affected by many device parameters such as gate capacitance, channel doping concentration, and gate material, the conversion equation from the gate voltage to the surface potential should incorporate all the values that could affect. Therefore, the following equation was used to calculate surface potential in conventional MOSFET with a polysilicon gate. S2 The calculated values from this equation were presented in Figure 4d of the main text, where q: quantity of electric charge, NA: channel doping concentration, si : permittivity of silicon, Cox: gate capacitance, and NPG: polysilicon gate doping concentration.
In order to solve this equation for calculating the sub-band separation, the average inter-peak voltage was replaced by VG-VFB. The calculated sub-band separation, which indicates valley splitting, shows similar trend with conduction band variation in ultra-thin-body silicon. S3 It is confirmed that the valleys split more, as the thickness of silicon nano-membrane decreases.
The amount of valley splitting is 70.2 meV when there is 2.5 nm of silicon, whose energy is around 3 kT, where k: Boltzmann constant and T: absolute temperature. Other devices show ~ 2 kT of valley splitting which is large enough to reveal RTQCE.

TEM and strain analysis
Accurate measurement of the thickness of the silicon nano-membrane and strain analysis were performed by HR-TEM. The HR-TEM was a Titan double cross-sectional corrected TEM whose resolution was point resolution of 0.08 nm and both information limit and STEM resolution of 0.07 nm. We used accelerating voltage 300 kV. In order to analyze strain in the silicon nano-membrane by measuring atomic distance, a high-resolution TEM image is required. When performing simple Fast Fourier Transform (FFT) and masking, which were explained in Figures 2a to 2c in the main manuscript, it was impossible to obtain re-constructed an image with high resolution. Figure S1a shows a TEM image of a 2.5 nm thick device. As it can be seen, it is not only difficult to measure the atomic distance from the original TEM data, but also the measured data may not be reliable. Therefore, we adopted inverse FFT technique.
Through the inverse FFT with applying a mask, atomic arrangement was clearly re-constructed as can be seen in Figure S1b.

AFM analysis -2D power spectral density
The silicon surface after iterations of thinning process was analyzed, showing low RMS surface roughness and fractal dimension close to two. Figure S2a shows 3D tilted view of AFM image which was performed on a thinned top silicon surface of a SOI wafer over a 10 μm × 10 μm area. The silicon surface has extremely flat surface with several hundred picometer roughness at maximum. 2D power spectral density (PSD) analysis was performed to characterize the silicon surface.
The RMS roughness and the fractal dimension decrease as thinning process is repeated. Such trend was confirmed in Figure S2b. In the plot of 2D PSD with respect to spatial frequency, the integration of the region below the data point line is proportional to the square of the RMS roughness. Two different polysilicon samples, deposited by low pressure chemical vapor deposition, were prepared for comparison purpose. The 2D PSD of silicon was much smaller than that of polysilicon.