Figure 2 | Scientific Reports

Figure 2

From: Fast Flexible Transistors with a Nanotrench Structure

Figure 2

Fabrication process for nano trench Si NM flexible RF TFTs by NIL.

Schematic illustration (left column), cross section structure (middle column) and corresponding microscopic images (right column) of nano trench Si NM flexible RF TFTs. (a) Defining a nano trench on a phosphorus implanted p− SOI substrate using NIL. (b) Dry etching to separate the n+ area in order to form a path of n+/p−/n+ from source to drain. (c) A partially completed TFT after undercutting the buried oxide to release the Si NM, which forms the active region and forming the source and drain contacts. (d) Flip transfer of the Si NM with the source and drain electrodes onto an adhesive coated PET substrate. (e) Dry etching to define the perimeter of the active region. (f) Deposition of an Al2O3 gate dielectric layers and gold gate electrodes above the trench. (g) Optical image of arrays of the bent TFTs on a PET substrate.

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