Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect.

In this paper, the SWCNT-FETs in double-gated structure have been fabricated by using a ferroelectric poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) polymer gate insulator to obtain the controllable hysteresis of drain current under different polarized states. The schematic of our SWCNT-FETs by ferroelectric gating (SWCNT-FeFET) device is shown in Fig. 1a and the optical micrograph of these SWCNT-FeFET arrays is shown in Fig. 1b. The transistor channel is made from a random SWCNT network composed of 98% semiconducting single-walled CNTs, which is connected by a source and drain electrodes with a 10 nm thick Cr layer and 50 nm thick Au layer. The P(VDF-TrFE) film is chosen as the top gate insulator due to its high dielectric constants 17 , isolation effect of moisture 18 and polarization properties [19][20][21][22] , which can compensate the current hysteresis arising from SWCNT networks and achieve a controllable hysteresis loop and threshold voltage of SWCNT channel under different polarized states. Meanwhile, the threshold voltage can be also tuned to desired values quantitatively by applying bottom gate voltage to control the carrier concentration in SWCNT network channel under the electrostatic doping effect. Meanwhile, the P(VDF-TrFE) as an ogranic polymer is soluble in ketones, which is usually used to remove photoresist in standard lithography process. Herein, we adopted the standard lithography process to achieve the graphics of organic polymers by dry etching process, which offers a great potential to the scaling down of the size of organic electronics and the compatibility with conventional CMOS process technology. Figure 1c shows the Raman spectrum of the SWCNT networks on the Si/SiO 2 substrate, from which typical G and 2D bands and almost no obvious D bands can be clearly observed, indicating good quality of SWCNT networks. A densely packed SWCNT network with a density of more than 100 nanotubes per square micron on the poly-L-lysine treated SiO 2 surface has been observed from the AFM image as shown in the inset of Fig. 1c, which is suitable for FET channel layer applications. From Fig. 1d, a symmetrical hysteresis behavior can be seen with two peak capacitance values observed at ±5 V under different voltage sweeping directions at the measurement frequency of 1.2 MHz, indicating the reversal of polarization and weakest intensity of polarization. However, the minimum capacitances have been found at ±20 V, which is induced by the saturated polarization. It demonstrates the typical hysteresis properties induced by the ferroelectric polarization of P(VDF-TrFE) films.   Fig. 2d is the measured structure with the bottom-gate electrodes applied by V BG . Compared the transfer characteristics by SiO 2 gating with and without P(VDF-TrFE) layer, the hysteresis window has been obviously reduced from 16.5 V to 7.5 V and the current has been also reduced by two orders of magnitude. The decrease of clockwise hysteresis window by SiO 2 back gating confirms the isolation effect of P(VDF-TrFE) films from the environmental water and oxygen molecules on the top surface of SWCNT networks. Meanwhile, the remaining clockwise hysteresis may be due to the charges already trapped at the surface between SiO 2 and SWCNTs. It is noted that both the clockwise hysteresis curves by SiO 2 back gating with and without P(VDF-TrFE) films are observed, which are obviously opposite to that by P(VDF-TrFE) top gating. The origin of the clockwise hysteresis by SiO 2 back gating can be due to the interference of moisture or oxygen from the surrounding environment and charge trapped at the surface between SiO 2 and SWCNT, which contributes to an unstable electrical performance. The conversion from clockwise hysteresis to anticlockwise one by P(VDF-TrFE) top gating is attributed to the ferroelectric polarization characteristics. The different polarized states controlled by the applied V TG induce the change of carrier density in the SWCNT channel and the type of carrier won't change until the reversal of polarization happens, which results in the anticlockwise hysteresis. It demonstrates that current hysteresis in a top-gate FET with a solution-processed SWCNT network is significantly suppressed and a tunable anticlockwise hysteresis has been achieved under the modulation of ferroelectric polarization. Figure 2f shows the output characteristics of the SWCNT-FETs by SiO 2 back gating, which shows the similar p-type semiconductors properties with that by P(VDF-TrFE) top gating.

Characterization of SWCNT-FeFETs.
Working mechanism of SWCNT-FeFET under the ferroelectric polarization. The SWCNT-FeFET working mechanism has been discussed as shown in the Fig. 3. In such P(VDF-TrFE) top-gated SWCNT-FETs, the ferroelectric layer has been used as the top gate dielectric layer with the SWCNT networks as the channel layer. When a negative V TG is applied to the top gate, the polarization of the ferroelectric film will be aligned upward with the protons (H+ ) aggregating at the top surface of P(VDF-TrFE) films, whereas the electronegative fluorine anions (F− ) oriented toward the surface between P(VDF-TrFE) films and the SWCNT networks. In this case, positive charges are induced into the SWCNT networks under the effective negative field effect of V TG . This results in the accumulation of holes in the p-type SWCNT network conducting channel to form a high conductance state, representing the ON state. The same working principle exists in the case that a positive V TG is applied to the top gate and electrons are induced in the SWCNT networks as the OFF state. The hysteresis behavior of the SWCNT-FeFETs as a function of top gate voltage is shown in Fig. 3. Considering the ferroelectric hysteresis    Fig. 4b. The hysteresis loop becomes enlarged when the maximum V TG increases from 10 to 20 V at a step of 2 V. The hysteresis window becomes larger with the increase of V TG sweeping range and a largest hysteresis window about 5.7 V has been achieved at V TG equal to 20 V as shown in the inset of Fig. 4b, which confirms that the origin of such hysteretic behavior is due to the polarization of the ferroelectric layer 23 . In order to understand the modulation effect on the threshold voltage by the ferroelectric polarization, the V THp and V THn are plotted as a function of the V TGmax under different sweeping ranges as shown in Fig. 4c. Increasing V TGmax sweeping ranges applied on the top gate electrodes induce an enhanced arrangement of dipoles within the P(VDF-TrFE) films, which results in the increase of carrier density in SWCNT networks due to the ferroelectric polarization property of P(VDF-TrFE) films 24 . More electrons or holes will be accumulated in the SWCNT networks resulting in an n-doping or p-doping effect and the increasing shift of the threshold voltage as shown in Fig. 4d. It demonstrates the modulation effect of the ferroelectrics on the threshold voltages.
It is found that V TH can be also continuously tuned by applying a bottom gate voltage (V BG ) in such double-gate configuration. A clear V TH shift with V BG increasing from − 30 to 30 V with a step of 10 V can be observed in the transfer curves of the P(VDF-TrFE) top-gated SWCNT-FETs under different V TG sweeping directions (Fig. 5a,b). It can be attributed to the applied V BG , which changes the charge concentrations in the channel and thus modifies the shift of the threshold voltages. From Fig. 5c,d, it can be seen that when the V BG changes from − 30 to 30 V, the induced charges in the channel varies from holes to electrons resulting in a p-doping shifting to n-doping with the V THp from 1.25 to − 4.9 V and V THn from 4.8 nearly to 0 V. As noted, precisely controlling the transistor threshold voltage for realizing high noise-margin and robust circuits remains to be challenging. Here, an external field effect by V BG has been proposed to continuously tune the threshold voltage of SWCNT networks, which helps SWCNT network based circuits to have a high immunity towards the electrical noise in a system 7 .

Discussion
The double-gated structural field effect transistors with SWCNT networks as active channel and solution processed P(VDF-TrFE) as top gating insulator have been achieved. The initial hysteresis behaviors of SWCNT networks caused by charge traps from the ambient environment can be effectively suppressed and a controllable hysteresis has been achieved under the polarization effect of P(VDF-TrFE). Meanwhile, controlling the threshold voltage of the SWCNT-FETs can also be achieved by modifying the polarized states of the top gate dielectric P(VDF-TrFE). Moreover, bottom gating induced electrostatic doping effects are found to be another effective way to continuously tune the threshold voltage in the SWCNT-FETs by modulating the doping level in the SWCNT channel. The tunable threshold voltage by the polarization of ferroelectric and the electrostatic doping effect of bottom gate voltage is highly beneficial for the transistor operation in robust circuits. Method Fabrication of double-gate SWCNT-FeFETs. Single crystal p-Si (100) substrate (2-3 Ω ·cm) was used as the bottom gate electrodes with upper 90 nm silicon oxide (SiO 2 ) bottom gate insulator by thermal growth. The S/D electrodes consisted of a 10 nm chrome (Cr) adhesion layer followed by 50 nm gold (Au) were patterned by standard photolithography procedures and deposited by electron beam evaporation. Then Poly-L-lysine (0.1% w/v in H 2 O, Sigma-Aldrich) solution was drop-cast onto SiO 2 surface for 5 min to functionalize the SiO 2 surface for SWCNT deposition, followed by immersing the substrate in 98% semiconductor-enriched SWCNT suspension (NanoIntegris Inc.) for 1 hour and a rinse with DI water and isopropanol to remove the excess solution. Then standard photolithography and the following oxygen plasma etching were used to define the channel region by removing the extra SWCNTs. At this time, a bottom-gated SWCNT-FET by SiO 2 gating has been fabricated. Then, the precursor solution by dissolving the P(VDF-TrFE) (70/30) pellets in Diethyl carbonate was spin-coated on the top of the SWCNT-FETs fabricated above. To improve the degree of crystallization, the as-prepared P(VDF-TrFE) films with 200 nm thickness were annealed at 135 °C for 30 min. In order to define the top gate electrodes, 50 nm thick Al were thermally evaporated on the top of P(VDF-TrFE) films before photolithographic patterning. Then, another standard photolithography was used to define the top gate electrode and aluminum etching solution was used to remove the Al without the protection of photoresist. Finally, oxygen plasma etching was used to remove the remnant photoresist as well as the organic ferroelectric films outside the top gate electrodes protection.
Characterization. In order to examine the surface morphologies of the as-prepared SWCNT network films, the microstructure and morphology of the SWCNT network films were observed by atomic force microscopy (AFM, SPA 500, Seiko Instruments Inc.) with taping mode. The capacitance-voltage (C-V) characteristics of Al/P(VDF-TrFE)/ITO structure has been investigated to exam the hysteresis properties of the P(VDF-TrFE) films. The electrical properties of the SWCNT-FeFETs by ferroelectric gating were measured by Aligent 1500 semiconductor characterization system. The current-voltage (I-V) characteristics of the SWCNT-FeFETs were measured with the top electrodes applied to a sweeping voltage in a closed hoop and the bottom electrode grounded.