Few-layer HfS2 transistors

HfS2 is the novel transition metal dichalcogenide, which has not been experimentally investigated as the material for electron devices. As per the theoretical calculations, HfS2 has the potential for well-balanced mobility (1,800 cm2/V·s) and bandgap (1.2 eV) and hence it can be a good candidate for realizing low-power devices. In this paper, the fundamental properties of few-layer HfS2 flakes were experimentally evaluated. Micromechanical exfoliation using scotch tape extracted atomically thin HfS2 flakes with varying colour contrasts associated with the number of layers and resonant Raman peaks. We demonstrated the I-V characteristics of the back-gated few-layer (3.8 nm) HfS2 transistor with the robust current saturation. The on/off ratio was more than 104 and the maximum drain current of 0.2 μA/μm was observed. Moreover, using the electric double-layer gate structure with LiClO4:PEO electrolyte, the drain current of the HfS2 transistor significantly increased to 0.75 mA/μm and the mobility was estimated to be 45 cm2/V·s at least. This improved current seemed to indicate superior intrinsic properties of HfS2. These results provides the basic information for the experimental researches of electron devices based on HfS2.


Theoretical calculation of the ballistic current in single-layer HfS 2
We used the simple ballistic model to evaluate the transport properties of single-layer HfS 2 . 2D k-plane with 3-fold valleys at M points were considered. Each valley assumed to have the parabolic and ellipsoidal conduction band with the E-k relation of = ℏ + .
where k l , m l , k t , m t are the wavenumbers and effective masses for longitudinal (transverse) direction.
The drain bias is high enough to ignore the drain injection. Fermi energy was only controlled by the gate bias not affected by the drain bias.
The small current towards the drain, is given by = , where electron density dn and velocity along the channel v channel are calculated as follows m c is the direction dependent effective mass and α is the angle between the channel direction and M-Γ direction. Figure 2 (a) indicates the dJ distribution in 2D k-plane by the contour plot. Next, small current dJ was integrated for k-space and summed for 3 valleys. For the ballistic limit, all electrons at the potential bottleneck have positive wave number. Then, electron states with negative velocity against the channel direction were assumed to be empty.
Finally, gate voltage was defined as the sum of the Fermi energy shift and the voltage applied to the gate insulator. Applied Voltage to the gate insulator was defined as . /0 = 1 2 3455 6 78 6 9 : /0 . Then, total gate voltage is . ; = < " =< 9 1 + 1 2 3455 6 78 6 9 : /0 . This E 0 was determined as the Fermi Energy for the calculated current density is set at 100 nA/µm (which is the off current for high performance logic circuits required by the International Technology Roadmap for Semiconductors).

Thickness and contrast evaluation of HfS 2 layers
We confirmed the layered exfoliation of HfS 2 on SiO 2 substrate. The optical image had a clear discrete colour variation from blue (thin) to white (thick). The CCD count rate along the white dotted line from A to B was also described. The counting values decreased in incremental steps from the substrate to thicker HfS 2 .
The AFM measurement showed triangular structure, and the smallest step size was estimated to be less than 0.9 nm. We could reasonably consider that the step indicate the single layer of HfS 2 .

Hydrophyte evaluation of HfS 2
The contact angles of water drops for HfS 2 , highly oriented pyrolytic graphene, SiO 2 , O 3 -cleaned SiO 2 , and HMDS-self-assembled monolayer (SAM)-treated SiO 2 were evaluated. The HfS 2 crystal surface showed strong hydrophobicity similar to graphene, which means that HMDS-SAM treatment is suitable for transferring not only graphene but also HfS 2 . Figure S2. Contact angle evaluation of HfS 2 , graphene, SiO 2 , and HMDS-SAM-treated SiO 2 The current properties of HfS 2 FET with SiO 2 /Si back gate operation are shown below. The on/off ratio is only 10 for a bias range of 0-20 V and the maximum drain current is 10 pA/µm at V GS = 20 V. This inferior modulation property of V GS is probably due to the defect traps and rough surface of the SiO 2 back-gate insulator deposited by plasma-enhanced chemical vapour deposition. Following these results, the device was fabricated with ALD Al 2 O 3 to improve the quality of the back gate insulator and that device has been reported mainly in this report.

Hysteresis characteristics of HfS 2 MOSFET
Here, we discuss the hysteresis characteristics of the HfS 2 FET for back-gated operation. Figure  S4 shows the logarithmic plot of the I D -V GS characteristics. The ∆V GS shift in the subthreshold region in the hysteresis characteristics was approximately 15 V.