Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals

High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm2/Vs field-effect mobility, high ION/IOFF of 2.3 × 107, small 110 mV/dec sub-threshold slope, and a low VD of 2.5 V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals.

for low DC standby power consumption. Notably, Sn (Group IV) has ns 2 np 2 electron configuration and directive sp 3 orbitals, which differ from those of Zn 7 . According to first principle quantum-mechanical calculations, the considerably high μ FE in SnO 2 TFT is caused by its overlapped s-orbitals even in an ns 2 np 2 configuration.

Results
To increase the transistor I ON and reduce the operation voltage, a high-dielectric-constant (high-κ ) gate insulator 12,15 was used for the TFT. Figure 1(a) shows the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a gate capacitor with top Aluminum (Al) electrode, high-κ hafnium-oxide (HfO 2 ), and bottom n + -Si. In the Al/HfO 2 /n + -Si capacitor, a small leakage current of 5.7 × 10 −7 A/cm 2 at 2 V was obtained at a capacitance density of 0.38 μ F/cm 2 . The high capacitance density yielded a low equivalent-oxide-thickness (EOT) of only 9.1 nm, which was due to the high-κ HfO 2 with a κ of 17. Figure 1(b) shows the transistor's drain current versus gate voltage (I DS -V GS ) characteristics of the SnO 2 /HfO 2 TFTs with 4.5 ~ 20 nm thick SnO 2 . The device with thick 20 nm SnO 2 failed to show proper pinch off I OFF due to very high conductivity, although the device has very high I ON . The device with 4.5 nm thick SnO 2 shows the best I ON /I OFF performance. Figure 1  low I OFF is required to reduce the DC standby power. The low SS with the mean value and standard deviation of 100.2± 19.4 mV/decade indicates the good oxide/semiconductor interface to turn on the transistor fast. The I ON showed an inversely proportional relation with gate length in a wide gate length TFT, a typical method to extract mobility correctly for Si MOSFET and metal-gate/high-κ MOSFET [29][30][31] . A remarkably high μ FE of 147 cm 2 /Vs is obtained with the mean value and standard deviation of 141.6 ± 11.5 cm 2 /Vs, which is higher than that of ZnO-based TFTs 3-20 and even higher than that of a CVD-grown multilayered MoS 2 MOSFET [21][22][23][24] . To reach high mobility, epitaxial growth of crystalline MoS 2 on a crystal substrate is needed. Unfortunately, the mobility is lower for CVD-grown MoS 2 25-28 than peeled-off flakes from crystals [21][22][23][24][25][26][27][28] . The lattice mismatch caused defects are the other major concern for circuit yield. In contrast, high mobility SnO 2 TFT is achievable on the amorphous substrate and free from lattice-mismatch defects. Such metal-oxide has already been used to manufacture TFT circuit for display. It is crucial to notice that the mobility of metal-oxide increases with increasing carrier density 7 . In the 4.5-nm-thick SnO 2 TFT, the high mobility is due to the high V G -induced carrier density 31 of ~10 13 cm −2 to screen out charged defects. This is also supported by the higher mobility with larger V G 7 , where induced carrier density increases with V G . In the thicker 7 ~ 20 nm SnO 2 devices with poor pinch off, the mobility is lowered by extra parallel conduction from non-depleted bulk SnO 2 . The mobility is lowered in 3.5 nm SnO 2 TFT due to stronger roughness scattering from top surface. Here the SnO 2 surface roughness is 0.39 nm, close to the HfO 2 roughness of 0.41 nm.
The high mobility SnO 2 TFT was further investigated using material analysis. Figure 2(a) shows the X-ray photoelectron spectroscopy (XPS) spectra from the Sn 3d and O 1s core level of the SnO 2 thin film. The Sn 3d peak corresponded to the oxidation state of Sn 4+ , and the O 1s peak was attributed to the O-Sn and O-H bonds. Thus, the chemical composition was determined to be Sn 4+ O 2 2− . The X-ray diffraction spectroscopy (XRD) pattern in Fig. 2(b) reveals the presence of a rutile phase in SnO 2 . An average grain size of 7.9 nm was obtained using the Scherrer's equation. Figure 2(c) shows the cross-sectional transmission electron microscopy (TEM) image of the SnO 2 /HfO 2 stack. A relatively uniform SnO 2 layer with an ultra-thin thickness of 4.5 nm was observed.
To thoroughly understand the cause of the high mobility in SnO 2 TFT, first principle quantum-mechanical calculations were used to investigate the electronic structures of SnO 2 and ZnO; ZnO has been extensively studied using the localized density functional theory (DFT) to reveal the mechanism that leads to its high mobility. The structures of both SnO 2 and ZnO semiconductors were successfully obtained using local density approximation plus U (LDA+ U) method with appropriate U p and U d value. The LDA+ U method compensates for the underestimation of the bandgap caused by a strong self-interaction by the DFT. The bandgaps of SnO 2 and ZnO were calculated to be 3.68 and 3.39 eV (Figure S1(a) and S1(b)), respectively, which are consistent with the experimental values of 3.6 and 3.4 eV, respectively. The contribution of each orbital in the conduction band minimum (CBM) of SnO 2 was investigated using density of state (DOS) analysis. The energy of valence band minimum was set to zero for convenience. As shown in Fig. 3(a), the upmost valence band was predominated by the O 2p orbitals, and the contribution from Sn was mostly from 5p orbitals. The lower conduction states near CBM were mostly derived from Sn 5s orbitals, whereas the O 2p orbitals contributed only in higher energy states. The Sn 4d orbitals did not give rise to the electron conducting property of SnO 2 because the antibonding interaction between Sn 4d and O 2p orbitals led only to the slight mixing of states at a deep valence band level. The DOS results of ZnO (Fig. 3(b)) were similar to those of SnO 2 . The major difference between the valence bands of SnO 2 and ZnO is the contribution of d orbitals. The upper valence bands (from − 6 to 0 eV) were composed of primarily of O 2p orbitals and slight mixing states from Zn 4s, 4p and 3d, whereas Zn 3d orbitals dominated in deeper states. In conduction band, Zn 4s was the major component near CBM while O 2p orbitals had little contribution at levels lower than 5 eV. Therefore, the high mobility of SnO 2 was attributed to the overlapping of s-orbitals, as with ZnO, although it had ns 2 np 2 configuration. This is further supported by the charge density distribution of SnO 2 shown in Figure S2(a), which has highly overlapped orbitals similar with those of ZnO in Figure S2(b). The highly overlapped orbitals of SnO 2 is related to large atomic radius, one row below Zn in the periodic table. From the results of DOS and charge density distribution, the higher mobility than the state-of-the-art ZnO TFTs 32-33 is attributed to the highly overlapped s-orbitals of SnO 2 .
The carrier effective mass is a major factor that may explain the higher mobility of SnO 2 than that of ZnO. The high electron mobility of n-type materials is caused by a deep curvature in CBM of band structure shown in Figure S1(a) and S1(b), which leads to a low effective mass of electrons. The calculated electron effective mass of SnO 2 was approximately 20% lighter than that of ZnO, indicating a faster electron transport in the SnO 2 conduction band.
In conclusion, this SnO 2 TFT device had a considerably high mobility, high I ON /I OFF , low SS, low operation voltage, and ultra-thin thickness. The low operation voltage is due to the high-κ gate dielectric with a high capacitance density. The low SS indicates the good gate dielectric and SnO 2 interface. The high I ON /I OFF is related to the high mobility to increase I ON and the ultra-thin thickness to decrease I OFF , where the high mobility is caused by strongly overlapped s-orbitals.

Methods
The SnO 2 TFTs were fabricated on a heavily doped n-type silicon (100) substrate. The 40-nm-thick high-κ gate HfO 2 and 20 ~ 3.5-nm-thick SnO 2 films were deposited by physical vapor deposition. Thicker 20 nm SnO 2 film was also deposited for X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) pattern analysis. Then the high-κ layer and SnO 2 film was annealed at 400 o C. Finally, the Al source-drain electrodes were thermally evaporated and patterned. The gate length and width are 50 ~ 150 μ m and 500 μ m, respectively. Therefore, the maximum process temperature for this device is 400 o C. The fabricated devices were characterized by XPS, XRD, TEM, C-V, and I-V measurements. All quantum-mechanical calculations were performed by Cambridge Sequential Total Energy Package (CASTEP) code. Structural optimization was performed on each model prior to calculating their electrical properties. The LDA+ U method is known to correct the strong correlation of metal oxides and is proven to be quite effective for ZnO. The calculations were carried out by using generalized gradient approximation (GGA) with LDA+ U.