Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

be considered 10 . The electron energy (electron temperature) can be much higher than lattice energy (lattice temperature) in semiconductor devices [9][10][11] , while the energy difference between electrons and lattices is governed by the energy relaxation (ER) time 12 . Experimental results showed that the ER time in a graphene device is about 1 ps, and the electron gas temperature varies from 400 K to 700 K when the lattice temperature is 300 K in single-wall carbon nano-tubes 13 . Moreover, a larger difference between the electron temperature and the lattice temperature in graphene could be found 14 .

Results
Theory. The aim of this study is to provide an explanation for gate-controlled Schottky barrier of a metal-graphene transistor on a silicon substrate reported in ref. 7. We thought that this modeling of the Schottky barrier height lowering effects could be used in any metal-semiconductor contact.
The device architecture of a top-gated graphene field-effect transistor can be simplified as the structure shown in Fig. 1, which is applicable for classical metal-graphene transistor or a metal-graphene transistor on a silicon substrate. The device architecture presented in ref. 7 could be equivalent to that in Fig. 1, when the gate-oxide-semiconductor structure can be treated as a parallel-plate capacitor (it implies that the electric field at the graphene/silicon interface perpendicular to the interface E G equals to zero in Fig. 1). The channel in such a top-gated GFET (Fig. 1) is divided into the source region and the drain region. It is assumed that the electrons are widely spread over the graphene in the drain region and the channel electron, enclosed by the rectangle ABCD in Fig. 1, have the Gauss's surface. The saturation point is defined as x = 0, and the electric field outside the graphene layer is set as zero due to the screen effect by channel electrons. In other words, such a structure shown in Fig. 1 can be treated as a parallel-plate capacitor (the gate and the graphene can be regarded as parallel-plate terminals). The total of charge density (the charge density in the gate plus the charge density in the graphene) should be zero, therefore the electric field in the outside region of such a parallel-plate capacitor is zero according to the Gauss law, which is denoted as E G = 0. Similar to the surface potential method for metal-oxide-semiconductor field effect transistor (MOSFET) 15 , the Gauss law is applied to the sides of the rectangle ABCD shown in Fig. 1 under saturation bias conditions, is the surface potential at x, x is the coordinate along the channel (as shown in Fig. 1), V G is the gate voltage, V FB is the flat band voltage, t G is the thickness of the graphene layer, t ox is the thickness of the gate oxide, q is the electron charge, ε G is the dielectric constant of the graphene, ε ox is the dielectric constant of the gate oxide, N D and N A are the donor and acceptor concentrations, respectively, n is the electron density, p is the hole densities. The surface potential in the channel can be expressed as 16 : is the channel surface potential at x, qV BI is the built-in potential energy from Fermi level of the source to the Fermi Level of the channel. Similar to the method in 16 , for p-type graphene, one obtains where E gg is the band gap of the graphene and E gg = 0 for monolayer graphene, qφ B0 is the SBH (initial barrier height without lowering), n A is the donor doping areal density in the graphene layer, k B is the Boltzmann constant, T is the temperature, and n ig is the intrinsic carrier areal concentration of graphene. Thus the derivation of Eq. 1 for p-type graphene under depletion approximation can be written as 16 : Using the boundary conditions V(0) = V sat (V sat , the saturation voltage at onset of the saturation region, the position of x = 0 is the separating point between the source and drain regions), V(Δ L) = V D (V D is the drain voltage, Δ L is the length of the saturation region), E(0) = E sat (E sat is the saturation channel electric field) 15 , Eq. 4 can be solved to obtain V(x) as, . Thus the channel electric field distribution can be determined as: In order to determine the effective channel length L E , the length of the saturation region Δ L is required, the channel potential can be solved at Note that the lateral electric field along the channel in the source region can be treated as the gradual channel approximation 17 and the source voltage is 0 V, thus into the Eq. 7, and one obtains For simplicity, the lateral electric field in the drain region along the channel can be treated to be linear 15 where L E = L -Δ L is the effective channel length. Solving Eq.1 with the boundary condition (Eq. 9), one obtains Thus the following is obtained: 1 nm, thus it is found that, for realistic GFETs, such a condition is satisfied in most cases. Eq. 10 and Eq. 11 can be simplified as

F u r t h e r m o r e , a s s u m i n g t h a t
. Therefore, Eqs 5, 6, and 8 can be further simplified as In a field-effect transistor, a lateral electric field in the channel not only results in a drift motion of electrons in the channel, but also changes their disordered thermal motion (the electron energy or electron temperature). Thus, the correlation between the electron temperature and lattice temperature in the channel of a transistor under the saturation bias conditions is given as 16 where μ e is the mobility of electrons, τ e is the ER time of electrons, v is the electron velocity, T L is the lattice temperature (device temperature), and E ch is the lateral electric field along the channel. Based on the gradual channel approximation, the effective SBH seen by the channel electrons when they obtain energy from the ER process can be written as where qφ B is the effective SBH. Eq. 18 clearly shows that the effective Schottky barrier height will be affected by the difference between the electron temperature and lattice temperature. Larger difference between the electron temperature and lattice temperature could cause the larger reduction in the Schottky barrier height. According to the electron energy relationship, electron temperature increases with the square of the lateral electric field, electron energy relaxation time, and electron mobility. A lateral electric field in the channel can be analytically determined On the other hand, for n-type graphene, we just need to replace all (N A ) with (-N D ) in above equations. Then the similar equations for n-type graphene can be obtained.
For the source-drain current, the following equation of Schottky diode current-voltage relationship 16 can be used where S is the contact area between the source (drain) electrode and the channel (graphene), h is the Planck constant, and m * is the effective mass of graphene. Therefore the source-drain current with consideration of the channel electrons ER can be written as

Discussion
In our simulation, main parameters are given as following. The dielectric constant of 2.4 is used for graphene 18 . The thickness of single layer graphene is 0.34 nm 19 . According to other reports that the work function of graphene is considered as 4.5 eV in 20 and 4.4 eV in 21 , the work function of graphene is considered as 4.5 eV in this paper 21 . The band gap of 1.12 eV is used for Si 16 . The relative dielectric constant of SiO 2 , Si, and the published electron affinity of SiO 2 and Si are 3.9, 11.9, 0.9 eV and 4.05 eV, respectively [e.g. 22 It was experimentally reported that the effective SBH between graphene and silicon in a graphene device strongly depends on the gate voltage 7 . Kim, T. G. et al thought that such a SBH lowering effect should originate from the image potential in silicon nanowire field effect transistors (FET), where as the experimentally extracted SBH of 0.5 eV is smaller than that of 0.55 eV from the simulation 8 , and the effective SBH could be expressed as 8,24 , where t s is the thickness of the nanowire, ε s is its dielectric constant of the graphene, qφ Bi is the effective SBH with consideration of the image force, the C 1 , C 2 , and C 3 are fitting parameters. And the channel surface electric field is 24  for the positive V D , significant larger that the above theoretically calculation value, which denotes that the image force can not give a good explanation on the experimental data of the gate controlled SBH. Therefore, the hot-electron effect is adopted to theoretically investigate the gate controlled SBH in graphene. In the following results, the different effects of the image potential and the ER of channel electrons on the SBH lowering are shown, and the comparison of simulation results with experimental results of silicon nano-wire FETs is given. Figure 2 shows the reduction in the SBH (or the SBH lowering), , caused by the image force (Eq. 22) and the ER ((Eq. 18)), respectively, as a function of the lateral channel electric field. In Fig. 2, the ER time of 0.8 ps at 300 K 26 Fig. 2 that the reduction of the SBH φ ∆ caused by the image force is around 0.078 eV at the channel electric field of 5 kV/cm, whereas the φ ∆ caused by the ER of channel electrons is around 0.019 eV. Fig. 2 proves the validity of the ER of channel electrons as the physical mechanism of the SBH lowering in field-effect transistor by comparing the difference of SBH lowering induced by the image force and ER of channel electrons with experimental results.
According to Eq.22, the SBH lowering ( φ ∆ ) caused by the image force is proportional to the square root of the gate voltage, which denotes that φ While the SBH lowering caused by the ER of electrons is proportional to the square of the gate voltage according to Eq. 18, which denotes that φ . The further comparison of the reductions in SBH calculated by the image potential (the ER of channel electrons) and extracted from experimental data in ref. 7 is given as following. Figure 3 shows that the square of the SBH reduction φ (∆ ) 2 and the square root of the SBH reduction ( φ ∆ ) as a function of the gate voltage (the symbols in Fig. 3 are the experimental data that come from Fig. 3 B in ref. [7], and the SBH value of 0.67 eV is used to estimate φ ∆ ). Although both methods for the SBH lowering using the image force and the ER of channel electrons could be used to explain the SBH lowering observed in the  experimental results, which is shown in Fig. 3. Experimental extracted φ ∆ ~ Vg has a slightly better linear fitting in comparison with the linearly fitting of φ (∆ ) 2 ~ Vg. The adjusted R-Square is 0.95557 for linearly fitting of φ ∆ to V G , and the adjusted R-Square is 0.95308 for linearly fitting of φ (∆ ) 2 to V G , which demonstrates that the SBH lowering caused by the ER of channel electrons agrees better with the experimental results.
For the SBH lowering in the graphene/p-Si contacts, the maximum field graphene/p-Si contact under the abrupt approximation can be written as 16  Figure 4 shows how experimental values of the φ (∆ ) 2 and φ ∆ change with the maximum electric field in the graphene/p-Si contact (the symbols in Fig. 4 are the experimental data and come from Fig. 2 C of ref. [27]). In Fig. 4, it is also clearly shown that there is a better linear fit between experimental extracted φ ∆ and E max in comparison with the curve of φ (∆ ) 2 and E max . The adjusted R-Square is 0.99584 when we linearly fit E max to φ ∆ , and the adjusted R-Square is 0.96622 when we linearly fit E max to φ (∆ ) 2 . It indicates again that the SBH lowering caused by the ER is more in accord with the experimental results. All above results show that modeling the SBH lowering by using the ER of channel electrons in semiconductor devices is consistent with experimental results.
In the following, we will discuss the detailed influence of the ER of channel electrons on the gate controlled SBH lowering. It should be noted that the saturation density of n-type doping in monolayer graphene is around 1 × 10 13 cm −2 28 and the net p-type doping in bilayer and monolayer graphene is around 2 × 10 13 cm −2 29 . It was reported in 30 that the saturation characteristic of top-gated GFET degrades with the channel length shrinking from 5.6 μ m down to 100 nm, and complete saturation can occur at the channel length of 5.6 μ m. The source and drain material of p-type silicon is used in the following calculations. It should be noted that the electron velocity in a graphene can reach 1 × 10 6 m/s 1 , thus the distance of electron transport in the graphene during 1 ps is 1 μ m. For the energy balance conditions, all channel length used in the following calculations is larger than 1 μ m. And V FB = 0 is chosen in the all calculations of this work. Figure 5 shows how the reduction of the SBH caused by the relaxation of channel electrons as a function of the gate voltage for different acceptor densities, where for larger acceptor doping in a GFET a larger gate controlled SBH lowering could be observed. From Fig. 5, it can be concluded that the effective SBH between graphene and electrode in a GFET decreases with the increasing of gate voltage, which clearly shows that the SBH lowering in a GFET can be modulated by applying different gate voltages due to the ER of channel electrons. Figure 6 shows how the reduction of the SBH caused by ER of electrons changes with the gate voltage for different drain voltages. The inset of Fig. 6 shows that the reduction in the SBH caused by the ER of channel electrons slightly increases with the drain voltage. Because the saturation voltage is independent on the drain voltage according to Eq.13 and the relative small change in the effective channel length is caused by the drain voltage according to Eq. 16, the drain voltage could hardly reduce the SBH according to Eqs. 18 or 19. Figure 7 shows that the reduction of the SBH caused by the ER of channel electrons as function of the relative dielectric constant and thickness of the gate oxide in a GFET. It is observed that the reduction of the SBH rapidly increases firstly with the relative dielectric constant of the gate oxide in a GFET, then approaches to a saturation value for the large relative dielectric constant (> 20), which implies that gate insulator materials with high relative dielectric constant (> 20) should be chosen for the best gate controlled SBH lowering effects in a GFET. Fig. 7 also shows the reduction of the SBH decreases with a thicker oxide since the saturation voltage and electric field decreases with the increasing of oxide thickness according to Eq. 13 and Eq. 12. Figure 8 shows how the reduction of the SBH between the graphene and electrode in a GFET changes with the channel length for different gate voltages under a given drain voltage. The reduction in the SBH firstly rapidly decreases with increasing channel length, then saturates with further increasing of channel length. It is because the strength of saturation electric field along the channel is the reciprocal of the effective channel length according to Eq. 12, under the approximation assumption of gradual channel. It should be noted that the reduction of the SBH is a reciprocal function of the square of the effective channel length according to Eq. 18 or Eq. 19, thus the reduction of the SBH rapidly deceases with the increasing of channel length. Such a reduction is too small to be observed when the channel length is large enough. The inset figure in Fig. 8 illustrates that a change in doping density for small acceptor doping in graphene (< 1 × 10 11 cm −2 ) have almost no effect on the effective SBH, but a change in doping density for larger acceptor doping in graphene (> 1 × 10 11 cm −2 ) could significantly affect the effective SBH.
Though the models presented in the previous literature work 31,32 could describe the current-voltage characteristics of GFETs, it is difficult to analytically formulate Schottky barrier height lowering effects. In these models, Figure 5. The reduction of the SBH as a function of the gate voltage with the HfO 2 layer thickness of 20 nm for different acceptor density. The channel length is 2 μ m, the drain voltage is 3 V, the electronic mobility is 1300 cm 2 V −1 s −1 , the ER time is 1 ps and the device temperature is 300 K. Figure 6. The reduction of the SBH as a function of the gate voltage with the HfO 2 layer thickness of 20 nm for different drain voltage. The inset figure shows the reduction of the SBH as a function of drain voltage when the gate voltage is 2 V. The channel length is 2 μ m, the drain voltage is 3 V, the acceptor density in graphene is 1 × 10 12 cm −2 , the electronic mobility is 1300 cm 2 V −1 s −1 , the ER time is 1 ps and the device temperature is 300 K.
Scientific RepoRts | 5:18307 | DOI: 10.1038/srep18307 many parameters have been used for Schottky barrier height lowering effect; where some fitting parameters have to be adopted to keep consistent with experimental results. Therefore, the lack of concise expression for the gate-controlled Schottky barrier height lowering effects limits the practical application of these methods. In our proposed model, main parameters still provide clear physical meanings, especially for the Schottky barrier height lowering effect, indicating that these model parameters could be expressed by device parameters, such as relative dielectric constant, channel density, doping density, and the energy relation time, which ensure device optimization design of the high-performance graphene field effect transistors. At the same time, due to general validity of electron transport of Eqs. 17 and 18 in various semiconductor materials, the proposed model could be extended to non-graphene materials and other device architectures only if the channel electric field is known. In others words, we can obtain similar conclusions by using the derivation of the channel electric field in other device architectures.

Conclusions
In conclusion, the effect of the ER (Energy Relaxation) of channel electrons on the SBH between graphene and electrode in a GFET has been theoretically investigated and physically modeled. The theoretical calculations agree well with experimental data reported in ref. [7,24,27]. The ER of channel electrons can result in a high electron temperature, thus causing a larger reduction in the SBH between graphene and electrode. Based on the energy Figure 7. The reduction of the SBH as a function of the relative dielectric constant of the gate oxide with 20 nm thickness. The channel length is 2 μ m, the acceptor density in graphene is 1 × 10 12 cm −2 the electronic mobility is 1300 cm 2 V −1 s −1 , the ER time is 1 ps and the device temperature is 300 K. Figure 8. The reduction of the SBH as a function of the channel length when the acceptor density in graphene is 1 × 10 12 cm −2 . The inset figure shows the reduction of the SBH in as a function of the acceptor density when the channel length is 2 μ m. The HfO 2 layer thickness is 20 nm, the electronic mobility is 1300 cm 2 V −1 s −1 , the ER time is 1 ps and the device temperature is 300 K.
Scientific RepoRts | 5:18307 | DOI: 10.1038/srep18307 conservation equation with the balance assumption, a physical model is built in this work to describe the gate controlled SBH lowering effects in a GFET under the saturation mode. The increases in the electron mobility and the ER time of channel electron will result in a linear increase in the reduction in the SBH according to the proposed model (Eq. 19). And the effects of parameters such as oxide thickness, oxide relative dielectric constant, channel length, drain voltage, and acceptor density are analyzed in detail. The drain voltage has slightly effect on the reduction of the SBH. The increase of the gate oxide thickness, the acceptor density in the graphene, and the channel length result in the decrease of SBH reduction magnitude. Whereas, increase in the dielectric constant of the gate oxide and the gate voltage result in obvious SBH reduction. All these results indicate that the effect of electron ER on the reduction in SBH should be seriously taken into account in GFETs with nano-scale dimension.