Interfacial Engineering of Semiconductor–Superconductor Junctions for High Performance Micro-Coolers

The control of electronic and thermal transport through material interfaces is crucial for numerous micro and nanoelectronics applications and quantum devices. Here we report on the engineering of the electro-thermal properties of semiconductor-superconductor (Sm-S) electronic cooler junctions by a nanoscale insulating tunnel barrier introduced between the Sm and S electrodes. Unexpectedly, such an interface barrier does not increase the junction resistance but strongly reduces the detrimental sub-gap leakage current. These features are key to achieving high cooling power tunnel junction refrigerators, and we demonstrate unparalleled performance in silicon-based Sm-S electron cooler devices with orders of magnitudes improvement in the cooling power in comparison to previous works. By adapting the junctions in strain-engineered silicon coolers we also demonstrate efficient electron temperature reduction from 300 mK to below 100 mK. Investigations on junctions with different interface quality indicate that the previously unexplained sub-gap leakage current is strongly influenced by the Sm-S interface states. These states often dictate the junction electrical resistance through the well-known Fermi level pinning effect and, therefore, superconductivity could be generally used to probe and optimize metal-semiconductor contact behaviour.


Device fabrication
Doped well devices: Experimental sample preparation began with a standard low resistivity (1-10 cm p-type) (100) 6" silicon wafer which underwent a blanket SiO 2 deposition, followed by photolithography to define regions for dopant implantation. Windows in the surface oxide were opened using a buffered HF solution before phosphorus ion implantation and activation anneal to give a surface doping concentration of N D =4×10 19 cm -3 . A second round of oxide deposition, photolithography and chemical etch was carried out in order to define the junction areas. After 2 % HF dip (30 s) the wafers were quickly rinsed and dried and loaded to the sputtering chamber. A thin oxide tunnel barrier was grown via an in-situ oxidation at 300 Torr and 550 °C for 10 minutes for Si-2 samples. For the Ar plasma treated sample we used 15 s Ar treatment at 900 eV. Aluminium was then deposited, patterned and etched to form the superconducting electrode and contact metal. The cooler geometry consisted of an electronically active region with dimensions 10 m by 25 m, a pair of circular central thermometer junctions, each with a diameter of 2 m, with two 9 m by 2 m cooler junctions either side, giving a combined cooling junction area of 72 m 2 .
Strained epi-layer devices: For the strained silicon sample, biaxial tensile strain was induced via lattice mismatch between silicon and the silicon-germanium alloy. As with the doped well devices, we used a standard low resistivity (1-10 cm p-type) (100) silicon wafer. Firstly, a linearly graded Si 1- x Ge x layer was grown with the germanium content x increasing from 0 to 0.22 over 2 m. This layer was relaxed to the lattice spacing of the silicon germanium alloy and the upper interface was relatively free from crystal dislocations as these were confined within the lower section of the layer. A constant composition layer of 500 nm Si 0.78 Ge 0.22 was deposited to ensure good material quality. Finally, a 30 nm silicon layer was grown, conforming to the lattice spacing of the alloy below. This layer was epitaxially doped to N D =4×10 19 cm -3 . The silicon was found to be under approximately 0.95% of tensile strain as confirmed by X-ray diffraction analysis. The mesa was patterned by photolithography followed by plasma etching. In the case of the cooler structures this created a raised rectangular pillar approximately 100 nm tall with lateral dimensions 148 m by 4 m. The active layer was confined within the top 30 nm, thus the degenerately doped silicon was effectively isolated and its geometry was well defined. The native oxide was removed using 1% HF before the thin oxide tunnel barrier was grown via an in-situ oxidation at 200 Torr and 550 °C for 10 minutes. Aluminium was then deposited, patterned and etched to form the superconducting electrodes and contact metal. Both the doped well and strained device designs adopted an array of interdigitated parallel junctions. This geometry both improves the quasiparticle thermalisation and reduces the series resistance of the silicon R sm which reduces Joule heating. Table 1: Device parameters. Dopant concentrations were confirmed by Hall measurements and R C was extracted from junction I-V measurements. Volume, and electron-phonon coupling factor, were not required when fitting the data for the Si-1 and Si-2 samples as described in section 4.

Electron Cooling measurements
Whilst the geometry and design of the electron coolers varied between devices, a generic layout is presented in figure 1 to illustrate the experimental setup. The cooler devices presented in this work utilised multiple junction coolers and a single, smaller double junction positioned symmetrically between the two coolers for electron temperature thermometry.
The cooler Sm-S junction pairs were connected in parallel and a range of biases were applied. Figure  1 illustrates current bias, but in the measurement both current and voltage were measured simultaneously and the nature of the bias (voltage/current) depended on the bias point due to the strong nonlinearity of the Sm-S junction. Simultaneously, the thermometer junctions were biased at optimum sensitivity using a high impedance battery powered current source and the voltage drop V T was amplified using a floating differential voltage amplifier. The cooler voltage sweeps were repeated for a set of bath temperatures T b and the thermometer junction voltage was calibrated against a RuO thermometer at V C = 0, where the electron temperature is equal to that of the surrounding bath T b . This is the standard procedure for junction thermometry [1]. See the calibration section of this document for further details.

Modelling
The cooling power of a junction is balanced against a number of heating mechanisms, principally the heat flow between the lattice phonons and the electron gas, mediated by the electron-phonon coupling. This is given by the equation = with being the cooled volume and the material specific coupling constant, which has been studied in previous work [2]. Additional heating power = is included to account for the Joule heating as a result of the semiconductor resistance R Sm , along with a term describing the fraction of power returned to the superconducting electrode via quasiparticle effects such as back-tunnelling and recombination in close proximity to the junction. [3,4].
The equilibrium state of these power flows is described by the heat balance equation which can be solved for electron temperature for a given cooler voltage. Here P c is the junction cooling as referred to in the main paper.

Electron-phonon coupling
The electron-phonon coupling heat flow P ph is typically calculated using the known volume and the coupling constant of the cooled material [5]. In this work, this procedure is followed for the strained samples. For the doped well samples the exact thickness is difficult to determine accurately as the doping profile arises from the implantation and annealing/activation step. Therefore, we determined P ph from electron heating measurement described below.
The electron-phonon coupling test device consisted of a long large area bar (200 m x 5 m) which was fabricated on the same wafer with the cooler devices. In the experiments a pair of thermometer junctions half way along the bar were used to record the electron temperature T e as a function of the applied Joule heating power P= P ph produced by electric current (this is the well-known hot-electron effect observed at low temperatures [1,2,6]). The electron thermometry was similar as in the electron refrigeration measurements for the cooler devices (see section 5 and also Figure 1). To generate a virtually continuous data set for P ph , which can be used at arbitrary bath temperature T b and T e , we measured electron temperature response to the Joule heating at several T b and then generated the electron-phonon thermal conductance e ph e dT dP G (5) from the data in the spirit of Ref. [2]. The result is shown in figure 2. We can observe that G e-ph follows closely to T 5 power law as expected for a disordered many-valley semiconductor [2]. To find P e-ph , when solving equation (4), we simply integrated the measured G e-ph between the limits of T e and T b to extract P e-ph as a function of electron temperature. This result was then scaled for the area of a specific cooler and used in (4), allowing us to accurately model the balance of heat mechanisms in the device. In this way, integration of (5) was used to experimentally determine P e-ph .

Figure 2:
Electron-phonon thermal conductance as a function of electron temperature (red dots). T 5 dependency is illustrated by the dashed line.

Thermometer Calibration
We biased the small area thermometer tunnel junctions with a small constant current (0.1-1 nA). The measured thermometer voltage V T at V C = 0, where the electron temperature is equal to that of the surrounding bath T b , produced a calibration curve such as that shown in the left panel of The junction thermometers typically become less sensitive at lower temperatures due to sub-gap leakage, power dissipation from the RF noise of the environment and heating from the thermometer bias current. These effects lead to saturation of the thermometer and the voltage no longer drops with bath temperature. However, during the electron refrigeration by the large cooler junctions, the parasitic heating effects are offset by the cooling power, so that the voltage response of the thermometer continues towards lower temperatures (see the right panel of figure 3). For this reason we use linear extrapolation to lower temperatures and lower thermometer probe voltages.
We also investigated an alternative calibration method called the isotherm method, which has been used successfully by other groups [7,8] and relies on comparing the measured data to calculated I-V curves using parameters extracted from a fit to a higher temperature measurement. The measured current-voltage data was superimposed on a series of theoretical isotherm curves generated from equation (1), using the parameters of the device under test. Each point of intersection between the experimental data and an isotherm yields the electron gas temperature in the semiconductor island at that particular cooler junction voltage. Figure 4 compares the results for the strained silicon device as determined using the current biased junction thermometry method and the isotherm method. The isotherm method is not very accurate at low biases, so we have not included low voltage results for the isotherm method. The agreement of the two methods is very good (see figure 4) and in the main paper we resort to the junction thermometry method.