Hall and field-effect mobilities in few layered p-WSe2 field-effect transistors

Here, we present a temperature (T) dependent comparison between field-effect and Hall mobilities in field-effect transistors based on few-layered WSe2 exfoliated onto SiO2. Without dielectric engineering and beyond a T-dependent threshold gate-voltage, we observe maximum hole mobilities approaching 350 cm2/Vs at T = 300 K. The hole Hall mobility reaches a maximum value of 650 cm2/Vs as T is lowered below ~150 K, indicating that insofar WSe2-based field-effect transistors (FETs) display the largest Hall mobilities among the transition metal dichalcogenides. The gate capacitance, as extracted from the Hall-effect, reveals the presence of spurious charges in the channel, while the two-terminal sheet resistivity displays two-dimensional variable-range hopping behavior, indicating carrier localization induced by disorder at the interface between WSe2 and SiO2. We argue that improvements in the fabrication protocols as, for example, the use of a substrate free of dangling bonds are likely to produce WSe2-based FETs displaying higher room temperature mobilities, i.e. approaching those of p-doped Si, which would make it a suitable candidate for high performance opto-electronics.

the Hall mobility has been found to increase from ,175 cm 2 /Vs at 60 K to 311 cm 2 /Vs at T 5 1 K at back-gate voltages as large as 100 V 18 . However, marked discrepancies were reported between the measured field-effect and the Hall mobilities 17 , which at the light of Refs. 11-13 could be attributed to underestimated values for the gate capacitances.
Similarly to past research on graphene, much of the current effort on TMD-based FETs is focused on understanding the role played by the substrates, annealing conditions and the work functions of the metallic contacts. For example, it was recently argued that most of the above quoted mobilities are determined by the Schottky barriers at the level of the current contacts which limits the current-density that can be extracted from these transistors. The authors of Ref. 19 argue that small Schottky barriers, and therefore nearly Ohmic contacts in TMD based FETs, can only be achieved through the use of metals with small work functions such as Sc. Furthermore, due to the detrimental role played by the SiO 2 substrates, Ref. 19 finds that the highest mobilities (,175 cm 2 /Vs) can be achieved in FETs built on ,10 nm (,15 layers) thick flakes. Thickness dependent mobilities were also recently reported for MoS 2 based transistors using polymethyl methacrylate (PMMA) as the gate dielectrics 20 . High performance TMD-based FETs have been claimed to have the potential to make a major impact in low power optoelectronics 5,[21][22][23] .
Here, to evaluate this assertion, we study and compare field-effect and Hall mobilities in field-effect transistors based on few-layered WSe 2 exfoliated onto SiO 2 , finding that they can display room temperature hole-mobilities approaching those of hole-doped Si 8 with a large ON to OFF ratio (.10 6 ) and sharp subthreshold swings (ranging from 250 and 140 mV per decade). This observation is remarkable given that i) carrier mobility is expected to be limited by the scattering from intrinsic 24 as well as substrate phonons, ii) the Schottky barriers at the contacts have yet to be optimized, and as we show iii) the presence of charge traps and disorder at the interface between WSe 2 and SiO 2 should limit the carrier mobility. Improvements in device fabrication, can lead to improved performance with respect to these values open promising prospects for optoelectronic applications. Figures 1a and b show respectively, a micrograph of a typical device, whose experimental results will be discussed throughout this manuscript, and the sketch of a four-terminal configuration for conductance measurements. Current source I 1 and drain I 2 terminals, as well as the pairs of voltage contacts 1, 2 and 3, 4 are indicated. As shown below, this configuration of contacts allows us to compare electrical transport measurements performed when using a 2-contact configuration (e.g. m FE ) with a 4-terminal one (e.g. R xy or the Halleffect). Figure 1b shows an atomic force microscopy profile and image (inset) from which we extract a flake thickness of ,8 nm, or approximately 12 atomic layers. We chose to focus on multilayered FETs because our preliminary observations agree with those of Refs. 19, 20, indicating that the highest mobilities are observed in flakes with thicknesses between ,10 and 15 atomic layers as shown in Fig. 1d. In addition, as argued in Ref. 5 multilayered flakes should lead to thin film transistors yielding higher drive currents when compared to transistors based on single atomic layers, possibly making multilayered FETs more suitable for high-resolution liquid crystal and organic light-emitting diode displays 5 . Our flakes were mechanically exfoliated and transferred onto a 270 nm thick SiO 2 layer grown on p-doped Si, which is used as a back gate. Throughout this study, we focus on devices with thicknesses ranging from 9 to 15 layers. Three of the devices were annealed at 150 uC, under high vacuum for 24 h, which as reported in Ref. 17, yields higher mobilities particularly at low temperatures. We found very similar overall  (I ds ), are indicated through labels I 1 (source) and I 2 (drain), while the resistivity of the device r xx was measured through either the pair of voltage contacts labeled as 1 and 2 or pair 3 and 4. The Hall resistance R xy was measured with an AC excitation either through the pair of contacts 1 and 3 or 2 and 4. Length l of the channel, or the separation between the current contacts, is l 5 15.8 mm while the width of the channel is w 5 7.7 mm. (b) Height profile (along the blue line shown in the inset) indicating a thickness of 80 Å , or approximately 12 atomic layers for the crystal in (a). Inset: atomic force microscopy image collected from a lateral edge of the WSe 2 crystal in (a). (c) Side view sketch of our field-effect transistor(s), indicating that the Ti/Au pads contact all atomic layers, and of the experimental configuration of measurements. (d) Room temperature field-effect mobility m FE as a function of crystal thickness extracted from several FETs based on WSe 2 exfoliated onto SiO 2 . The maximum mobility is observed for ,12 atomic layers. response among the non-annealed samples, as well as among the annealed ones. Figure 2a shows the extracted field-effect current I ds as a function of the back gate voltage V bg for several fixed values of the voltage V ds across the current contacts, i.e. when using a 2-terminal configuration. From initial studies 7 , but in contrast with Refs. 25,26, WSe 2 is expected to show ambipolar behavior, i.e. a sizable current resulting from the accumulation of either electrons or holes at the WSe 2 /SiO 2 interface due to the electric field-effect. Although we have previously observed such a behavior, all FETs studied here show a rather modest electron current (i.e. saturating at ,10 28 A) at positive V bg values in contrast also with samples covered with Al 2 O 3 , see Ref. 26. Therefore our samples behave as if hole-doped (i.e. sizeable currents only for negative gate voltages). At room temperature the minimum current is observed around V bg < 0 V while the difference in current between the transistor in its ''ON''-state with respect to the OFF-one (on/off ratio) is .10 6 . For all measurements, the maximum channel current was limited in order to prevent damaging our FETs. The subthreshold swing SS is found to be ,250 mV per decade, or ,3.5 times larger than the smallest values extracted from Si MOSFETs at room temperature. Figure 2b shows the conductivity s 5 I ds l/V ds w (from a), as a function of V bg for several values of V ds . As indicated in the caption of Fig. 1 the separation between the current contacts, is l 5 15.8 mm while the width of the channel is w 5 7.7 mm. As seen, all curves collapse on a single curve indicating linear behavior, despite the claimed role for Schottky barriers at the level of contacts 19 . See also the Supplemental Information section for linear current-voltage characteristics for the range of excitation voltages used. Figure 2c: the field-effect mobility m FE can be evaluated in the standard way by normalizing by the value of the gate capacitance (c g 5 12.789 3 10 29 F/cm 2 ) the derivative of the conductivity with respect to V bg . As seen, m FE increases sharply above V bg < 2 V reaching a maximum of ,305 cm 2 /Vs at V bg ,220 V, decreasing again beyond this value. Alternatively, the mobility can be directly evaluated through the slope of I ds as a function of V bg in its linear regime, and by normalizing it by the sample geometrical factors, the excitation voltage V bg and the gate capacitance c g , yielding a peak value m FE < 302 cm 2 /Vs. We have observed m FE values as high as 350 cm 2 /Vs (see results for sample 2 below). These values, resulting from two-terminal measurements, are comparable to those previously reported by us for multi-layered MoS 2 , where we used a four-terminal configuration to eliminate the detrimental role played by the less than ideal contacts 27 . Figures 3a, b, c, and d show respectively, I ds as a function of V bg for several values of V ds , the corresponding conductivities s as a function of V bg , and the resulting field-effect mobility as previously extracted through Figs. 2c and d. All curves were acquired at T 5 105 K. As seen, at lower temperatures s(T, V bg ) still shows a linear dependence on V ds although lower Ts should be less favorable for thermally activated transport across Schottky barriers. In fact, we collected similarly linear data sets at T , 105 K. At T 5 105 K, m FE displays considerably higher values, i.e. it surpasses 650 cm 2 / Vs (accompanied by a reduction in the SS down to ,140 mV per decade). However, as seen in Fig. 3a, lower temperatures increase the threshold gate voltage V t bg required for carrier conduction. Below we argue that this is the result of a prominent role played by disorder and/or charge traps at the interface between WSe 2 and SiO 2 instead of just an effect associated with the Schottky barriers. Large Schottky barriers are expected to lead to non-linear current I ds as a function of the excitation voltage V ds characteristics, with a sizeable I ds emerging only when V ds surpasses a threshold value determined by the char- , between drain and source contacts. Notice that the ON/OFF ratio approaches 10 6 and subthreshold swing SS ,250 mV per decade. We evaluated the resistance R c of the contacts by performing also 4 terminal measurements (see Fig. 7 a below) through R c 5 V ds /I ds -r xx l/w, where r xx is the sheet resistivity of the channel measured in a four-terminal configuration. We found the ratio R c /r xx < 20 to remain nearly constant as a function of V bg . (b) Conductivity s 5 S l/w, where the conductance S 5 I ds / V ds (from (a)), as a function of V bg and for several values of V ds . Notice, how all the curves collapse on a single curve, indicating linear dependence on V ds . As argued below, this linear dependence most likely results from thermionic emission across the Schottky-barrier at the level of the contacts. (c) Field effect mobility m FE 5 (1/c g ds/dV bg as a function of V bg , where c g 5 e r e 0 /d 5 12.789 3 10 29 F/cm 2 (for a d 5 270 nm thick SiO 2 layer). (d) I ds as a function of V bg , when using an excitation voltage V ds 5 5 mV. Red line is a linear fit whose slope yields a field-effect mobility m FE < 300 cm 2 /Vs. acteristic Schottky energy barrier w, as seen for instance in Ref. 28. But according to Figs. 2b and 3b, s is basically independent on V ds above a threshold gate voltage, even at lower temperatures. Figure 4a shows I ds as a function of V bg for several temperatures and for the crystal shown in Fig. 1a. Fig. 4b shows the resulting fieldeffect mobility m FE as a function of T as extracted from the slopes of I ds (V bg , T). m FE is observed to increase, reaching a maximum of ,650 cm 2 /Vs at T , 100 K, decreasing subsequently to values around 250 cm 2 /Vs at low temperatures. Orange markers depict m FE for a second, annealed sample whose Hall mobility is discussed below. This decrease is attributable to extrinsic factors, such as chemical residues from the lithographic process, since annealing the samples under high vacuum for at least 24 h considerably increases the mobility at low Ts 17 , as will be illustrated by the results shown below for a second sample annealed in this way. Figure 4c shows m FE as a function of V bg for several temperatures (as extracted from the curves in a). All curves show a maximum at a V bg -dependent value. As seen, the main effect of lowering T is to increase the threshold back-gate voltage V t bg for carrier conduction. In WS 2 , by using ambipolar ionic liquid gating, which heavily screens charged defects, the authors of Ref. 29 were able to estimate the size of its semiconducting gap, given roughly by the difference between the threshold voltages required for hole and electron conduction respectively, or ,1.4 V. The much larger V t bg values observed by us in WSe 2 is attributable to intrinsic and extrinsic effects, such as vacancies and charge traps, which limit the carrier mobility becoming particularly relevant at low temperatures, see discussion below. At first glance, at low gate voltages r would seem to follow activated behavior with a small activation gap. On the other hand at high temperatures and high gate voltages, r displays metallic like behavior, usually defined by hr/hT . 0. Magenta line is a fit to a simple linear-dependence on temperature, suggesting either an unconventional metallic state or most likely, phonon scattering.

Results and Discussion
As observed in Figs. 4a and c, the threshold gate-voltage V t bg required to observe a finite s increases from ,5 to ,35 V as T is lowered from 300 to 5 K. In order to clarify the dependence of V t bg on T, we assume that V t bg is dominated by disorder at the interface between WSe 2 and SiO 2 which leads to charge localization. To illustrate this point, in Fig. 5 we plot s(T) as function of T 21/3 since from past experience on Si/SiO 2 MOSFETs, it is well known that spurious charges intrinsic to the SiO 2 layer [30][31][32] , in addition to the roughness at the interface between the Si and the glassy SiO 2 33 , produces charge localization leading to variable-range hopping conductivity: s(T) 5 s 0 exp(-T 0 /T) 1/(11d) where d is the dimensionality of the system, or d 5 2 in our case 34 . As seen in Fig. 5, one observes a crossover from metallic-like to a clear two-dimensional variable-range hopping (2DVRH) conductivity below a gate voltage dependent temperature; red lines are linear fits. At lower gate voltages, the 2DVRH regime is observed over the entire range of temperatures. Therefore, despite the linear transport regime and the relatively large mobilities observed in Figs. 1 through 4, this plot indicates very clearly, that below V t bg the carriers in the channel are localized due to disorder. Notice that similar conclusions were also reported from measurements on MoS 2 35 . Although, at the moment we do not have a clear experimental understanding on the type and on the concomitant role of disorder in these systems (which would allow a deeper theoretical understanding on the origin of the localization), the above experimental plot is unambiguous in revealing the predominant conduction mechanism for gate-voltages below a threshold value. Now, we are in position of qualitatively explaining the T-dependence of V t bg : thermal activated processes promote carriers across a mobility edge which defines the boundary between extended electronic states and a tail in the density of states composed of localized electronic states. At higher temperatures, more carriers are thermally excited across the mobility edge, or equivalently, can be excited across the potential well(s) produced by disorder or charge traps, therefore one needs lower gate voltage(s) to untrap the carriers. Once these carriers have moved across the mobility edge, they become mobile and, as our results show, respond linearly as a function of the excitation voltage V ds . Finally, as V t bg increases with decreasing T the number of carriers is expected to decrease continuously since they become progressively localized due to the suppression of thermally activated processes which can no longer contribute to carrier detrapping. This is clearly illustrated by Fig. 4b, where one sees an increase in mobility, due to the suppression of phonon scattering, leading to a maximum in the mobility and to its subsequent suppression upon additional cooling. Therefore, at higher temperatures and for gate voltages above the threshold, where one observes a metallic-like state, one has two competing mechanisms at play upon cooling, i.e. the tendency to localization/suppression of carriers which is unfavorable to metallicity, and the suppression of phonon scattering. Suppression of phonon scattering is the only possible explanation for the observed metallic behavior. Hence, one must conclude that this metallic behavior ought to be intrinsic to the compound, but disorder-induced carrier localization dominates s at lower temperatures.
Although, as Figs. 2 and 3 indicate, the conductivity s as measured through a two-terminal configuration, is linear on excitation voltage V ds when V bg . V t bg , it was discussed at length that the electrical conduction through the drain and source contacts can by no means be ohmic 19,36 . In effect, a Schottky barrier of ,770 meV is expected as the difference in energy between the work function of Ti, or 4.33 eV, and the ionization energy of WSe 2 , or ,5.1 eV 37,38 . The linear, or apparent ohmic regime presumably would result from thermionic emission or thermionic field emission processes. According to thermionic emission theory, the drain-source current I ds is related to the Schottky barrier height w SB through the expression: Where A is the area of the Schottky junction, A* 5 4pem*k B 2 h 23 is the effective Richardson constant, e is the elementary charge, k B is the Boltzmann constant, m* is the effective mass and h is the Planck constant 39 . In order to evaluate the Schottky barrier at the level of the contacts, in the top panel of Fig. 6 we plot I ds normalized by the square of the temperature T 2 as a function of e/k B T and for several values of the gate voltage. Red lines are linear fits from which we extract the w SB (V bg ). Notice that in the top panel of Fig. 6 the linear fits are limited to higher temperatures since at lower temperatures one observes pronounced, gate dependent, deviations from the thermionic emission theory. The bottom panel of Fig. 6 shows w SB (V bg ) in a logarithmic scale as a function of V bg . Red line is a linear fit from whose deviation we extract the size of the Schottky barrier 19 , or W ,16 meV, indicating a much better band alignment than originally expected. It is perhaps possible that the Eq. (1) might take a different form for layered two-dimensional materials, for example, in such compounds one might need a temperature pre-factor distinct from T 2 . We attempted the use of different temperature pre-factors such as T or T 3/2 , but it does not improve the linearity of log(I ds /T a ) (with 2 $ a $ 1) as a function of ek B /T. In fact, an arbitrary T pre-factor, would not be theoretically justifiable at the moment. Having said that, one has to be very careful with the extraction of the Schottky barrier through this common approach, since the two-terminal measurements contain contributions from both the contacts and the conduction channel. As discussed above, the channel underdoes disorder-induced carrier localization, thus masking the true behavior of the conduction across the contacts. Notice for example, how in Fig. 5 2DVRH fits the behavior of the s(T) over the entire range of temperatures when V bg 5 220 V, while in Fig. 6, thermionic emission can describe the behavior of I ds /T 2 as a function of T 21 only when T . 125 K. Therefore the values of w SB (V bg ) extracted here should be taken with caution.
In Figure 7, we compare the above field-effect mobilities with Hall mobility measurements on a second, vacuum annealed flake of similar thickness. Figure 7 a shows the four-terminal sheet resistivity, i.e. r xx 5 wV ds /lI ds as a function of V bg . r xx was measured with a lock-in technique, for gate voltages where the voltages V 12 or V 34 were in phase with the excitation signal. We also checked that any pair of voltage contacts produced nearly the same value for r xx , indicating a nearly uniform current throughout the channel. r xx increases very rapidly, beyond 10 9 V as V bg R 0 V. Also the out-of-phase component of the measured AC signal becomes very large as V bg R 0 limiting the V bg range for our measurements. Figure 7b displays the measured Hall signal R xy as a function of the magnetic field H at T 5 50 K and for several values of V bg . Red lines are linear fits from which we extract the Hall constant R H 5 R xy /H 5 1/ne. In the same Fig. 7b we also indicate the extracted values for the Hall mobilities, m H 5 R H / r xx , at different gate voltages. Notice that for T 5 50 K and V bg 5 70 V one obtains, in this annealed sample, a m H value of ,676 cm 2 / Vs. Figure 7c shows the density of carriers n H 5 1/eR H as a function of V bg for several Ts. Red lines are linear fits from which we extract the slope n H /V bg 5 c g */e, where c g * is an effective back-gate capacitance: in the absence of extrinsic charged defects at the WSe 2 /SiO 2 interface, c g * should be equal to the previously quoted gate capacitance c g . Solid evidence for the existence of ionized impurities acting as hole traps at the interface is provided by the linear fits in Fig. 7c which intercepts the n H 5 0 axis at finite threshold gate voltages V t bg . This confirms that practically all holes generated by applying a gate voltage smaller than V t bg remain localized at the interface. Figure 7d shows a comparison between m FE (magenta and blue lines) and m H (red markers) as extracted from the same device at room temperature. The blue line was measured after thermally cycling the FET down to low temperatures. Notice how V t bg increases after thermally cycling the sample, thus suggesting that strain at the interface, resulting from the difference between the thermal expansion coefficients of SiO 2 and WSe 2 , also contributes to V t bg . Therefore, strain would seem to be an additional factor contributing to the mobility edge. Notice also that both mobilities initially increase as a function jV bg j, reaching a maximum at the same V bg value, decreasing subsequently as the back-gate voltage is further increased. Figure 7e shows m H as a function of T for several values of V bg . Notice how m H (T R 0 K) is suppressed at low gate voltages due to the charge localization mechanism discussed above. m H is observed to increase as T is lowered, requiring ever increasing values of V bg . V t bg , but decreases again below T ,5 K. A fit of m H (T, V bg 5 260 V) to AT 2a yields a , (1 6 0.1). Finally Fig. 7f displays the T-dependence of the ratio between the measured and the ideal geometrical gate capacitance (c g * 5 se)/c g where s corresponds to the slopes extracted from the linear-fits in Fig. 7c. For a perfect FET this ratio should be equal to 1, i.e. the only charges in the conducting channel should be those resulting from the electric field-effect. Therefore, one can estimate the carrier mobility m i for the nearly ideal device, i.e. with the ideal geometrical capacitance, through m i 5 c g */c g m H , which at T 5 300 K would lead to V bgdependent mobilities ranging from 350 up to 525 cm 2 /Vs. This rough estimate does not take into account scattering processes resulting from for example, other sources of disorder within the channel. In agreement with Ref. 40, this indicates that in our WSe 2 FETs the main scattering mechanism limiting the carrier mobility are not phonons, but ionized impurities and disorder, or that phonon scattering would still allow mobilities approaching, and probably surpassing, 500 cm 2 /Vs at room temperature. In p-doped Si the hole-mobility is observed to saturate at a value of ,475 cm 2 /Vs for doping levels below ,10 17 per cm 3 , while a doping concentration of 10 19 per cm 3 yields mobilities of ,200 cm 2 /Vs as observed here 8 . Therefore, our work indicates that if one was able to improve the FET fabrication protocols, by minimizing the disorder such as interface roughness, spurious ionized impurities and dangling bonds at the interface, WSe 2 could match the performance of p-doped Si, thus becoming suitable for specific applications 5 with the added advantage of miniaturization, since the starting point would be just a few atomic layers.
Notice that the m FE values extracted here at higher Ts would be overestimated if one considers the value of the gate capacitance extracted from the Hall effect, i.e. it would be two to three times larger than the expected geometrical capacitance, thus implying 2 to 3 times smaller values for m FE . A number of reports on TMDs 16,19,20 suggest room temperature field-effect mobilities ranging from 300 to ,700 cm 2 /Vs for MoS 2 based FETs subjected to ''dielectric engineering''. However, taken together with the debate in Refs. 11, 12  concerning the true value of the gate capacitance in dual gated FETs, our study suggests that those values should be carefully re-examined by performing four-terminal Hall-mobility and/or capacitance measurements.
In the Supplemental Information, we show the Raman spectra of WSe 2 whose main Raman modes are observed to sharpen considerably as the number of layers decrease, implying a pronounced increase in phonon lifetimes. Possibly, the main source of disorder in WSe 2 is stacking disorder, which is progressively eliminated as one decreases the number of layers. This also implies a high degree of inplane crystallinity. On the other hand, polarized Raman indicates that most Raman modes in WSe 2 are mixed modes, i.e. composed of in-plane and out-of-plane lattice vibrations, which might affect the strength of its electron-phonon coupling.
Although a gate-voltage dependent Raman study has yet to be performed in WSe 2 , in both single-layer 41 and bi-layer 42 graphene, it was observed that the gate-voltage can tune the interaction between phonons and the charge carriers, leading to changes in the amplitude and in the line-width of the Raman spectra. A similar gate-voltage dependence in WSe 2 might reveal reduced electron-phonon scattering therefore explaining the higher room-temperature Hall mobilities observed here. Notice, that monolayer TMDs have been predicted to display strong piezoelectricity 43 , suggesting that these materials are prone to a strong coupling between lattice degrees of freedom and an external electric field.

Conclusions
In summary field-effect transistors based on multi-layered p-doped WSe 2 can display peak hole Hall-mobilities in excess of 200 cm 2 /Vs at room temperature. This value increases by a factor .3.3 when the temperature decreases to ,100 K. The carrier density as a function of the gate voltage, as extracted from the Hall-effect, indicates larger than expected gate capacitances thus implying an excess of spurious charges in the channel. Therefore, one should be cautious when quoting values for the field-effect mobility by using the geometrical gate capacitance value. These spurious charges, in addition to disorder at the WSe 2 /SiO 2 interface, leads to carrier localization and to a concomitant mobility edge, which manifests itself in an increasing threshold gate voltage for carrier conduction and, at a fixed gate voltage, to a concomitant decrease in carrier mobility upon cooling (resulting from an increase in the threshold gate voltage). When using Ti:Au for the electrical contacts one obtains a remarkably small value for the size of the Schottky barrier, although thermionic emission theory can only properly fit the transport data at higher temperatures.
We emphasize that our results indicate that WSe 2 displays what seemingly are the highest Hall mobilities observed so far in TMDs, particularly among FETs based on few-layered TMDs exfoliated onto SiO 2 and remarkably, without the use of distinct or additional dielectric layers. The Hall mobility values observed here surpass, for example, the m H values in Ref. 17 for MoS 2 on HfO 2 or the fieldeffect mobilities of thicker multilayered MoS 2 flakes 5 on Al 2 O 3 . This indicates that WSe 2 has the potential to display even higher carrier mobilities, particularly at room temperature, through the identification of suitable substrates (flatter interfaces, absence of impurities and dangling bonds, etc), as well as contact materials. A major materials research effort must be undertaken to clarify the density of point defects (e.g. vacancies, intercalants) in the currently available material and on how to decrease their density. However, our study reveals that WSe 2 has the potential to become as good if not a better material for optoelectronic applications than, for instance, multi-layered MoS 2 5 . Recently, Ref. 44 reported the performance of multi-layered WSe 2 FETs, composed of WSe 2 atomic layers transferred onto a h-BN substrate using graphene for the electrical contacts as well as ionic liquid gating. Remarkably, despite the complexity of this architecture, originally intended to improve the overall performance of multi-layered WSe 2 FETs, the simpler devices reported here, still display considerably higher mobilities. We believe this is an import- induced by the back gate voltage as a function of V bg . Red lines are linear fits from which, by comparing the resulting slope s 5 n/V bg 5 c g */e (c g * is the effective gate capacitance). (d) Field-effect m FE (magenta and blue lines) and Hall m H 5 R H /r xx (red markers) mobilities (where r xx 5 R xx w/l, w and l are the width and the length of the channel, respectively) as functions of V bg at T 5 300 K. (e) Extracted Hall mobility m H as a function of T and for several values of V bg . m H increases as T is lowered, but subsequently it is seen to decrease below a V bg -dependent T. (f) Ratio between experimentally extracted and the ideal, or geometrical gate capacitances c g */c g (black markers) and the mobilities m i 5 c g */c g m H (V bg 5 260 V) (red markers) as functions of T. m i are the mobility values that one would obtain if the gate capacitance displayed its ideal c g value in absence of spurious charges in the channel.
www.nature.com/scientificreports ant piece of information for those considering the development of electronic or optoelectronic applications based on transition metal dichalcogenides.

Methods
WSe 2 single crystals were synthesized through a chemical vapor transport technique using iodine as the transport agent. Multi-layered flakes of WSe 2 were exfoliated from these single crystals by using the ''scotch-tape" micromechanical cleavage technique, and transferred onto p-doped Si wafers covered with a 270 nm thick layer of SiO 2 . Prior to transferring the WSe 2 crystals onto the SiO 2 layers, these were cleaned in the following way: SiO 2 was sonicated for 15 min in acetone, isopropanol and deionized water, respectively. It was subsequently dried by a nitrogen gas flow. For making the electrical contacts 90 nm of Au was deposited onto a 4 nm layer of Ti via e-beam evaporation. Contacts were patterned using standard e-beam lithography techniques. After gold deposition, the devices were annealed at 200uC for ,2 h in forming gas. Atomic force microscopy (AFM) imaging was performed using the Asylum Research MFP-3D AFM. Electrical characterization was performed by using a combination of sourcemeter (Keithley 2612 A), Lock-In amplifier (Signal Recovery 7265) and resistance bridges (Lakeshore 370) coupled to a Physical Property Measurement System. The Raman spectra were measured in a backscattering geometry using a 532.1 nm laser excitation. For additional details see the Supplementary Information.