Electron transport of WS2 transistors in a hexagonal boron nitride dielectric environment

We present the first study of the intrinsic electrical properties of WS2 transistors fabricated with two different dielectric environments WS2 on SiO2 and WS2 on h-BN/SiO2, respectively. A comparative analysis of the electrical characteristics of multiple transistors fabricated from natural and synthetic WS2 with various thicknesses from single- up to four-layers and over a wide temperature range from 300 K down to 4.2 K shows that disorder intrinsic to WS2 is currently the limiting factor of the electrical properties of this material. These results shed light on the role played by extrinsic factors such as charge traps in the oxide dielectric thought to be the cause for the commonly observed small values of charge carrier mobility in transition metal dichalcogenides.

We present the first study of the intrinsic electrical properties of WS 2 transistors fabricated with two different dielectric environments WS 2 on SiO 2 and WS 2 on h-BN/SiO 2 , respectively. A comparative analysis of the electrical characteristics of multiple transistors fabricated from natural and synthetic WS 2 with various thicknesses from single-up to four-layers and over a wide temperature range from 300 K down to 4.2 K shows that disorder intrinsic to WS 2 is currently the limiting factor of the electrical properties of this material. These results shed light on the role played by extrinsic factors such as charge traps in the oxide dielectric thought to be the cause for the commonly observed small values of charge carrier mobility in transition metal dichalcogenides.
T he emerging class of atomically thin semiconducting materials formed by transition metal dichalogenides (TMDCs) is showing a plethora of complementary properties to those of graphene that are of interest to fundamental and applied research. These materials are uniquely suited to study the superconducting phase transition in the extreme two-dimensional limit inherent to atomically thin systems [1][2][3][4] . At the same time TMDCs have a band gap which is essential for transistor applications and which could enable a new class of atomically thin photo-transistors. For example WS 2 has a direct band gap of 2 eV in single layer form [5][6][7][8] and has already shown great promise as a flexible transistor with field effect mobilities comparable to the best liquid crystals and on/off ratio of the current exceeding 10 6 9 . Understanding the limiting factors of the electrical properties of TMDCs is an open quest and a stepping stone for accessing novel physics in these systems.
The typical values of charge carrier mobility measured in thin WS 2 flakes are always much lower than those measured in bulk material 2,4 . This behaviour has been interpreted as due to defect states in the SiO 2 substrate leading to the localization of charge carriers in TMDCs and a small charge carrier mobility 10 . To probe the intrinsic electrical properties of TMDCs it would be necessary to measure electrical transport in either suspended structures or in transistors fabricated on clean substrates with fewer impurities than typically present in SiO 2 . An ideal choice for such a substrate is hexagonal boron nitride 11 , which is a preferred substrate for high quality graphene transistors since it has a very low concentration of charge scattering impurities and is atomically flat 12 . To date such a study has not yet been conducted and the consequent lack of knowledge is limiting the potential impact of TMDCs on fundamental and applied research. Furthermore most of the studies conducted so far have been limited to just MoS 2 , while other TMDCs such as WS 2 have not yet received much attention, whereas they might be better suited than MoS 2 for a given application.
Here we present the first study of the electrical properties in WS 2 transistors fabricated on different dielectrics (i.e. SiO 2 and h-BN/SiO 2 ) and using synthetic as well as natural WS 2 . The comparative analysis of the electrical characteristics of these transistors studied in the temperature range from 300 K down to 4.2 K shows that in all cases electrical transport takes place via hopping conduction through localized states 13,14 . At low temperature (T , 20 K) we observe peaks of the conductance as a function of back-gate voltage and source-drain bias due to inelastic tunnelling in the impurity states with sub-gap energy. These results show that intrinsic disorder rather than extrinsic factors such as defect states in the oxide dielectric is limiting the electrical properties of WS 2 and more generally TMDCs.

Results
Thin flakes of WS 2 were obtained by mechanical exfoliation of flakes from synthetic crystals onto p-doped Si/SiO 2 substrate that serves as a back gate (for natural WS 2 see supporting information). Thin flakes are first identified with the aid of optical microscopy and their thickness is subsequently determined by atomic force microscopy (AFM) and Raman spectroscopy. The fabrication of WS 2 transistors on h-BN and subsequent encapsulation in h-BN is carried out using the dry transfer method first developed for graphene 12 . This consists of exfoliating WS 2 onto a substrate coated by water soluble polymer and PMMA. After dissolving in water the soluble polymer, the free WS 2 / PMMA bilayer is aligned onto previously exfoliated h-BN (,20 nm thick) on p-doped Si/SiO 2 . The substrate is then heated up to melt the PMMA and secure contact between WS 2 and h-BN and the PMMA is subsequently removed in acetone. Electrical contacts to WS 2 are fabricated using standard electron beam lithography, thermal evaporation and lift-off of Cr/Au (5/70 nm). Figure 1a shows an AFM measurement of a thin WS 2 flake with a fold in the upper left corner highlighted by a dashed line. A statistical study of the height measured in areas which include the step edge at WS 2 /SiO2 (region A) and the folded corner (region B) shows a comparable step height of <1.6 nm in A and <1.3 nm in B, see Figure 1b. Since the thickness of a monolayer WS 2 flake is <0.65 nm 8,15 we conclude that this flake is a bilayer. A comparative plot of the Raman spectra (see methods) for WS 2 with different layer numbers shows marked differences depending on the specific thickness of the flake, see Figure 1c. More specifically it is known that the peak with low Raman shift (<350 cm 21 ) is a convolution of two Lorentzians ( Figure 1d) whose positions change as a function of the layer number 16 . One Lorentzian is due to the second order longitudinal acoustic phonon mode (2LA(M)) corresponding to collective oscillations of the atoms in the plane, and this gives a Raman peak at 352.7 cm 21 in single layer WS 2 . The second Lorentzian is given by the in-plane optical phonon mode (E 1 2g C ð Þ) representing the inplane counter oscillations of W and S atoms in the lattice. Finally the out-of-plane optical phonon mode (A 1g (C)) representing the out-of-plane oscillations of W and S atoms gives a Raman peak at 416.6 cm 21 . A plot of the relative wavenumber shift (Dn that is the difference between the 2LA(M) and A 1g (C)Raman peaks) for a large number of flakes with various thicknesses shows that Dn changes in a discrete way according to the number of layers which have been independtly measured with AFM, see Fig. 1e. Finally, upon increasing the number of WS 2 layers the position of the 2LA(M) and E 1 2g C ð Þ peaks redshift monotonously, whereas the A 1g (C) peak blue shifts as previously shown 16 , see Figure 1f.
Having established a reliable procedure to identify the layer number of WS 2 flakes we now turn to investigate the electrical transport properties of this material. The source-drain current vs. bias voltage characteristics (I-V) of WS 2 transistor devices are always highly nonlinear and upon performing current-bias annealing, a linear I-V around zero voltage bias is attained (see Figure 2a  Counts (a.u.) 340 350 360 400 420 440 Counts (a.u.) Raman shift (cm -1 )  which these non-linearity occur suggest a different origin for this phenomenon, that is the possible presence of an oxide barrier at the WS 2 /Cr interface which can be electrically broken upon applying a large voltage bias as shown in Figure 2a. In the following we only consider the analysis of electrical transport measurements in devices after bias-annealing. Figure 2b-d show the room temperature field effect transistor (FET) transfer characteristics, that is the gate voltage (V g ) dependence of the conductivity (s), for monolayer WS 2 on SiO 2 (Figure 2b), four-layer WS 2 sample on a SiO 2 ( Figure 2c) and four-layer WS 2 sample on a h-BN/SiO 2 (Figure 2d). In all cases we observe that the conductivity has a large on-off ratio typical of semiconducting materials, with a finite threshold voltage. However we find that the field effect mobility (m) is always larger in WS 2 on h-BN than in WS 2 on SiO 2 (0.23 cm 2 V 21 s 21 for 1L-WS 2 /SiO 2 , 17 cm 2 V 21 s 21 for 4L-WS 2 /SiO 2 and <80 cm 2 V 21 s 21 for 4L-WS 2 /h-BN/SiO 2 in Figure 2(b-d)). A large hysteresis is also present in s(V g ) for WS 2 on SiO 2 but is fully suppressed when WS 2 is on h-BN/SiO 2 . Similar hysteresis in I-V have also been reported in graphene and is commonly attributed to dopants present in the SiO 2 dielectric 17,18 .

Discussion
For all the measured devices we find that the temperature dependence of s(V g ) shows a pronounced suppression of the value of s upon lowering the temperature as expected for a semiconducting material, see Figure 3a. In these devices we apply a large enough value of gate voltage such that the charge carriers are directly injected from the metal contacts into the conduction band of WS 2 . In this limit the relevant energy scale dominating the temperature dependence of the zero-bias resistance is the difference between the Fermi energy and the conduction band edge of the n-doped semiconductor (i.e. WS 2 ) 20 . A plot of s as a function of T 21 at V g 5 60.5 V reveals that from 260 K down to 100 K the conduction takes place by thermally activated charge carriers, i.e. s(T) 5 s 0 exp(2de/2k B T) with de the activation energy and k B the Boltzman constant. The values of de estimated from a fit of s(T) for 50 V , V g , 60 V are in the range 0.109 eV , de ,0.113 eV and change linearly with V g , see inset in Figure 3b. These values of de are compatible with the voltage bias range over which non-linear I-V are measured (see blue curve in Figure 2a) suggesting that de is the energy from the Fermi level to the conduction band edge (E c ), i.e. de 5 E c 2 E F which is also much larger than the Schottky barrier height (<100 meV).
The smooth dependence of de on V g demonstrates that for sub-gap energies the Fermi level can be continuously tuned by means of a gate voltage throughout the defect induced states. To estimate the density of defect states we consider the equivalent gate capacitance of these WS 2 transistors that is the series of the gate oxide capacitance (C ox ) and defect states capacitance Knowing that the oxide capacitance per unit area is where q is the unit of charge and D(E) is the density of defect states which we estimate to be 3.12 3 10 37 J 21 m 22 .
The dominant role of disorder induced states with sub-gap energies becomes fully apparent when considering a fit of the low temperature s(T) in logharitmic scale in terms of T 2p with p critical exponent, see Figure 3c. This study reveals that p 5 1/3 gives the best fit stemming for non-interacting Mott variable range hopping 13    T 0 . Furthermore T 0 is found to fluctuate from <100 K to <4000 K in a small gate range (from V g 5 50.5 V to 52 V, corresponding to an energy window of just 0.25 meV). Consequently the estimated localization radius in WS 2 increases from 1.8 nm to 17 nm. These observations indicate that the sub-gap impurities states have peaks of narrow energy band-widths dominating electrical transport for sub-gap energies. Another prominent feature evident in the temperature dependence of s(V g ) is the emergence of peaks for T , 100 K with decreasing amplitude for T , 20 K, see Figure 3a. At the same time the differential conductance as a function of source-drain bias and gate voltage at T 5 4.2 K (Figure 4a) shows that these peaks shift their position as a function of voltage bias. These observations suggest that charge transport at sub-gap energies occurs through inhomogeneous charge puddles and localized states in WS 2 . Since we observe a similar s(V g ) behaviour in a variety of samples independently of (1) the WS 2 flakes aspect ratio, (2) the WS 2 layer number and (3) the dielectric environment (WS 2 /BN/SiO2, see supplementary information) we conclude that the localized states dominating electrical transport in WS 2 at sub-gap energies are intrinsic to the WS 2 and not extrinsic such as defect states in the dielectric.
To estimate the localization radius (j) we consider electrical transport measurements of a representative 4L-WS 2 in which the peaks of s(V g ) are spaced by an average gate voltage AEV g ae < 1.13 V corresponding to 0.17 meV, see bottom graph in Figure 4. In this device the peaks of s at fixed V g as a function of source-drain bias (V) are spaced by an AEVae < 11 mV, which for a channel length of 350 nm corresponds to a threshold electric field E T 5 3.14 3 10 4 V/m. This value of E T together with the observed average peak separation of 0.17 meV gives a localization region of diameter 2j 5 5.4 nm which is consistent with the extracted value of the localization radius j from the analysis conducted on the temperature dependence of s(V g ).   Finally we note that Coulomb blockade cannot account for the observed peaks of s(V g ). Indeed, if we assume a charging energy in our devices of Ec , 40-50 meV estimated directly from the stability diagram shown in Figure 4, we extract a diameter d , e 2 /4e 0 e r Ec , 20-40 nm for the confining regions (e 5 1.610 219 C, e 0 5 8.8510 212 F/ m and e r 5 (e vac 1 e BN )/2 5 2.5 with the dielectric constant for vacuum and BN e vac 5 1 and e BN 5 4). Given the dimensions of the conductive WS 2 channel, our devices would consist of 100-1000 charging regions (i.e. (length 3 width)/d 5 (350 nm 3 1500 nm)/ d). The stability diagram of such an array of charging islands would consist of many overlapping Coulomb diamonds which are not observed in our measurements. An indication of the underlying physical process originating these peaks of s(V g ) is given by the temperature dependence of s(V g ) presented in Figure 3a: we alwasy observe that the amplitude of the peaks decreases upon lowering the temperature. This behaviour has been previously reported in other semiconducting systems 21,22 and it is a fingerprint of inelastic tunnelling which in WS 2 occurs through the sub-gap impurity states.
In summary we have presented the first systematic study of the intrinsic electrical properties of thin WS 2 flakes. By comparing the I-Vg of transistors fabricated using two different dielectric environments (i.e. (1) WS 2 on SiO 2 and (2) WS 2 on h-BN/SiO 2 ) we find that hopping through localized states dominate electrical transport over a wide temperature range (T , 100 K). This intrinsic disorder has a finite density of states at sub-gap energies which contribute with inelastic tunnelling to electrical transport. These results demonstrate the dominant role played by intrinsic disorder over extrinsic factors such as defect states in the oxide dielectric as a limiting factor of the electrical properties of WS 2 .

Methods
Materials. Synthetic WS 2 was purchased from Lowerfriction.com.
Measurement techniques. The Raman spectra where measured with a Renishaw spectrometer using an excitation laser with a wavelength of 532 nm, focused to a spot size of 1.5 mm diameter and 1 mW incident power. These measurements were performed in air and at room temperature.
Electrical measurements. The electrical transport measurements were performed in constant voltage configuration with excitation voltage smaller than k B T, with k B Boltzmann constant. The differential conductance was measured using the lock-in technique.