Introduction

Silicon photonics has open new opportunities to meet the growing computational and data communications demands in today’s world by offering a cost-effective and scalable platform1. However, the photonic memory is still a missing building block in current silicon platforms. While there are several technologies that may be used for enabling photonic memories, to the best of our knowledge, this component has not yet been included in any Process Design Kit of CMOS foundries offering either Multi-Wafer Project runs or custom fabrication. Such a device may be essential for numerous applications but particularly in the emerging fields of neuromorphic computing and programmable photonics2. In these scenarios, the number of cycles an integrated photonic memory can undergo could be a critical metric for applications requiring high-cyclability, such as in situ neural network training3,4.

Over the past few years, various technologies, mainly phase change materials (PCMs), ferroelectrics and charge-trapping memories, have been explored for implementing photonic memories5,6. PCMs stand out for a dramatic change in their refractive index between material phase states, enabling devices with ultra-compact footprint and thereby showing a high potential for large-scale integration. Furthermore, most of the PCMs considered for photonics could be monolithically integrated in silicon platforms.

Chalcogenide-based photonic memories have arisen as a promising approach, primarily due to their non-volatile switching capability, which has been used for developing different photonic in-memory computing architectures7,8,9,10,11,12. However, one of the limitations of chalcogenides is the relatively poor endurance performance that has been demonstrated in hybrid photonic integrated devices, from typically ∼103 switching cycles6 up to 20,000 cycles13.

As an alternative to chalcogenides, vanadium dioxide (VO2) has the potential to convert into an appealing candidate to build photonic memories with an ultra-compact footprint by exploiting the hysteretic response of its refractive index variation with temperature14. VO2 could pave the way for faster and more energy-efficient devices due to its much lower switching temperature compared to chalcogenides, although at the expense of a volatile nature15. Nevertheless, the possibility for a non-volatile switching behavior at room temperature has also been recently reported16. In this work, we report a high-endurance ultra-compact VO2/Si photonic volatile memory showing a record cyclability of up to 107 write/erase cycles with speed and energy consumption outperforming chalcogenide-based non-volatile photonic memories5,6. The volatile nature of our proposal makes it suitable for applications where frequent switching is required, rather than long-term storage applications.

The proposed memory is shown in Fig. 1a, and it comprises a standard 220 × 500 nm silicon waveguide loaded with a 3 µm-long and 40-nm-thick VO2 patch deposited by molecular-beam epitaxy (MBE)15. The device works at 1550 nm and for the transverse magnetic polarization. The memory is programmed by using optical pulses to photothermally drive the VO2 between a low-loss insulating phase (erased memory state) and a high-loss metallic phase (written memory state). The simulated performance of the device is shown in the supplementary note 1. Figure 1b shows an optical image of the fabricated device. To hold the memory state, the optical power of the programming pulses is adjusted to fall within the hysteresis loop of the VO2 metal-to-insulator transition, as depicted in Fig. 1c. Nevertheless, microheaters could also be used to provide the holding temperature.

Fig. 1: Device scheme and working principle.
figure 1

a Working principle of our VO2/Si photonic memory operated by programming (write/erase) optical pulses. b Optical image of the fabricated device. c Sketch of the memory operation between written/erased states by exploiting the hysteretic response of the VO2 insulating-to-metal phase transition.

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Results

Endurance measurements

To demonstrate the maximum write/erase cycles our memory can undergo before it shows degradation signals, we repeated the write/erase cycle in the programming signal, illustrated in Fig. 1, with a period of 100 µs. The period was chosen so it was the lowest possible using our set-up to achieve the required optical power to operate the memory. We took a 5-cycle trace every second, which corresponds to a difference among traces of 104 cycles. Both write and erase optical pulses had a duration of 1 µs, while the state of the memory was held by using just 180 µW.

Figure 2 shows the cyclability tests for evaluating the endurance performance with an optical contrast of ∼2.6 dB between the written/erased states. The memory operation was successfully proven over 106 cycles [Fig. 2a–c]. Above this value, the optical contrast was gradually decreased due to optical misalignment and drifts in the experimental set-up. However, after realignment, the optical contrast between states was recovered, as shown in Fig. 2a, thus demonstrating a record value exceeding 107 cycles. It is important to notice that even after this huge number of cycles, the device continued working correctly. Moreover, the distribution of the optical transmission readout, shown in Fig. 2d, revealed a remarkable accuracy of ±0.11 dB in the erased state and ±0.085 dB in the written state for the standard deviation.

Fig. 2: Endurance measurements record.
figure 2

a Memory operation demonstrating more than a million cycles and just limited by misalignment. b Stable operation over 106 cycles before misalignment. c Detailed view of one of the traces showing 5 write/erase cycles with its corresponding programming pulse. d Distribution of the optical transmission readout after 4 × 106 cycles.

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Speed and energy consumption performance

In order to evaluate the potential programming speed and energy consumption, we applied a single optical pulse with the shortest duration (~100 ns) available by our setup into a smaller photonic memory of just 1 µm length. Figure 3 shows the transmission performance when injecting optical pulses with increasing energy. The switching time is reduced from 28 to 12 ns for the VO2 insulator-metal phase transition (writing process) when the energy pulse increases but at the expense of a longer switching time for the VO2 metal-insulator phase transition (erasing process) that increases from 36 to 208 ns. Hence, an energy pulse of 24 pJ was sufficient to switch back and forth the VO2 patch with switching times as fast as 24 and 36 ns, respectively.

Fig. 3: Switching speed and energy consumption performance.
figure 3

Switching operation by applying 100 ns-long optical pulses with increasing energies into smaller photonic memory of just 1 µm length. The ∼200 ns delay between the injecting pulse and output response is mainly caused by the external components and fiber used in the setup.

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Figure 4 depicts a comparison between different technologies employed for photonic memories such as chalcogenides, memristors, and charge-trapping, in terms of programming energy consumption and endurance. More details of the compared works are detailed in the supplementary note 2. Our VO2/Si memory approaches the ultra-low energy consumption of memristor technology but showcases four orders of magnitude increase in endurance. On the other hand, compared to the most used chalcogenide employed in photonic memories, Ge2Sb2Te5 (GST), our experimental results lead to a switching energy density of 0.4 aJ nm−3 to write the state, which is one order of magnitude lower than experimental state-of-the-art GST photonic memories (8 aJ nm−3) and even lower than the theoretical limit of GST (1.2 aJ nm−3)17.

Fig. 4: Programming energy vs endurance comparison.
figure 4

Programming energy consumption vs endurance of our work compared with other technologies such as chalcogenides6,13,21,25,26,27,28,29,30 (blue circle), charge-trapping memories31 (red square) memristors6,32 (black star) and other VO2 memories14 (green hexagon).

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Following the same procedure as in reference17, we can estimate the theoretical energy density limit to write the state in VO2. Considering the latent heat18,19, H = 235 J cm−3, the specific heat capacity20, C = 3 J cm−3 K−1 and the temperature where the complete transition to metal occurs T = 65 °C, we obtain a programing energy density of H + C ΔT = 0.31 aJ nm−3, where ΔT = 65–25 °C. However, in our memory device, such a temperature increase is lower since the programming process occurs from the holding temperature instead of the room temperature. Therefore, latent heat is only required to finish the transition and the theoretical energy density for programming a VO2 memory would be H = 0.23 aJ nm−3, which is near to our experimental value.

Discussion

In this work we have reported an ultra-compact VO2/Si photonic memory with a record endurance of up to 107 cycles. Furthermore, we have also demonstrated the potential for operating the memory with speeds of a few nanoseconds and energy consumption of a few picojoules. This result implies a huge increase in endurance from previous works and a significant reduction in programming energy consumption. To contextualize these values, in an application where the memory is erased and written with a frequency in the range of kHz, current photonic memories based on chalcogenides would only endure a few seconds before they experience a functionality degradation8,21. Moreover, most chalcogenide-based photonic hardware employed for neural network applications uses the offline learning approach4. In this procedure, the training of the neural network is done in the usual manner, computing the weights and biases via a backpropagation algorithm in a computer22. After that, the weights and biases are written onto the chalcogenide patches. Although this method is very useful in several cases, it does not offer any energy consumption or speed enhancement throughout the entire training process. Moreover, fabrication imperfections may imply deviations from the original (digital) parameters, resulting in a reduction of accuracy from the simulated model, the so-called ‘reality gap’23. In contraposition to this approach, in the in situ training24 or online training4, the photonic hardware is used to carry out the training. This approach would imply a substantial energy consumption reduction of neural network training, external computing tasks would be minimized, and fabrication imperfections would not affect the transfer of the digital weights to the analogic weights in the hardware (the ‘reality gap’ would not be present). In this regard, VO2 is positioned as a potential candidate for in situ training thanks to its high endurance and low programmable energy requirements. To summarize, our device could offer a promising solution for applications requiring memory functionality with high-cyclability together with low-power and fast-speed operation.

Methods

Experimental set-up

A contra-directional pump and probe technique was used to carry out both the endurance measurements and the energy and speed performance. A low-power continuous wave signal at 1565 nm was used to readout the change of the memory, whereas an externally modulated signal at 1550 nm was employed for programming and holding the state of the memory. The programming signal was modulated via an electro-optical modulator and amplified using an erbium-doped fiber amplifier. After pump (programming signal) and probe (readout) signals propagated through the sample, high-speed photodetectors were used to measure them with an oscilloscope. Moreover, one additional photodetector was used to obtain the chip transmission for real-time monitoring. Both input and output fibers were manually aligned, and the light was coupled onto the chip through grating couplers.

Fabrication process

The silicon photonic structures were fabricated on a standard silicon-on-insulator (SOI) sample with a top layer of 220-nm-thick silicon with a 3-µm-thick buried oxide layer. E-beam lithography was employed to pattern the silicon structures onto a negative tone resist. The patterning was transferred into the SOI sample by employing plasma-reactive ion etching (ICP-RIE). The VO2 structures were defined using the same e-beam lithography process onto a positive tone resist, with a subsequent development of the exposed areas using an MBIK:IPA bath. Then, a 40-nm-thick VOx layer was grown using MBE, followed by a lift-off process using MBIK:IPA in an ultrasonic bath. Then, polycrystalline VO2 was formed by carrying out an annealing in forming gas at 450 °C for 30 min. Finally, the VO2/Si structures were covered with a 700-nm-thick SiO2 cladding deposited using plasma-enhanced chemical vapor deposition at 200 °C.