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Towards efficient ESD protection strategies for advanced 3D systems-on-chip

Nature Reviews Electrical Engineering volume 1, pages 429–431 (2024)Cite this article

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2.5D/3D technologies require designers to reduce electrostatic discharge (ESD) protection of the internal I/O interfaces. To avoid over-design of ESD protection, designers require a more fundamental understanding of the ESD events that occur at this level. Here we present insights, practical guidelines and research directions for circuit designers and suppliers of bonding tools.

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Fig. 1: Die size has crucial role in ESD events.

References

  1. Chen, W. C. et al. How to protect advanced CMOS technologies with thin Si substrates against ESD events. imec https://go.nature.com/3Ryrz47 (2024).

  2. Beyne, E. et al. Imec demonstrates die-to-wafer hybrid bonding with a Cu interconnect pad pitch of 2μm. imec https://go.nature.com/45v5Csm (2024).

  3. Chew, S. A., De Vos, J. & Beyne, E. Wafer-to-wafer hybrid bonding at 400-nm interconnect pitch.Nat. Rev. Electr. Eng. 1, 71–72 (2024).

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  4. Lin, S. H. et al. Toward 0V ESD protection in 2.5D/3D advanced bonding technology. In IEEE Symposium on VLSI Technology & Circuits (2024).

  5. Industry Council on ESD Target Levels. White Paper 2, part II, revision 1.1 https://www.esdindustrycouncil.org/ic/en/ (2023).

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Acknowledgements

The authors acknowledge the contributions of W.-C. Chen, F. Gijbel, S.-H. Chen, Geert Van der Plas, E. Beyne and P. Wambacq.

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Authors and Affiliations

  1. imec, Leuven, Belgium

    Shih-Hsiang (Shane) Lin, Marko Simicic & Nicolas Pantano

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  1. Shih-Hsiang (Shane) Lin
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  2. Marko Simicic
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  3. Nicolas Pantano
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Correspondence to Shih-Hsiang (Shane) Lin.

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Lin, SH.(., Simicic, M. & Pantano, N. Towards efficient ESD protection strategies for advanced 3D systems-on-chip. Nat Rev Electr Eng 1, 429–431 (2024). https://doi.org/10.1038/s44287-024-00071-4

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  • DOI: https://doi.org/10.1038/s44287-024-00071-4

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