The unification of metal–oxide–semiconductor field-effect transistors (MOSFETs) with the concept of universal Turing machines in modern computer science marked a substantial milestone in the advance of digital electronics and technology. The desire to minimize the size and power requirements of computers demanded faster and more compact electronic circuits1. Moreover, Gordon Moore’s prediction that the number of transistors on a chip would double approximately every two years spurred semiconductor industries to compete in a race to adhere to this trend, known as Moore’s law2. This marked the beginning of an era dedicated to achieving maximal scaling in size and power efficiency of semiconductor chips, with the number of transistors per chip escalating from a few thousand to billions in less than five decades3. At present, scaling in semiconductor technology encompasses two primary aspects: (1) scaling based on system-level integration to augment the transistor count per chip and to incorporate additional functionalities into a system-on-a-chip and (2) scaling focused on the individual dimensions, structure and density of transistors4.

To facilitate scaling based on system-level integration, several semiconductor industries have developed various 3D integrated circuit (IC) packaging techniques5 and integration solutions6, such as Intel’s Foveros technology7 and TSMC’s 3DFabric, which utilize system-on-integrated-chips technology8. This arena of scaling thrives on innovations in technologies like wire bonding, through-silicon vias, through-glass vias, face-to-face chip stacking, flip-chip and the ThruChip interface9. These technologies enable increased interconnect bandwidth, enhanced performance, power and area, and potentially reduced costs, especially when stacking chiplets10. Conversely, the International Roadmap for Devices and Systems predicts that future process nodes will require highly parallel 3D architectures, achievable only through the sequential stacking of individual devices on top of one another11. Note that the term ‘node’ is not used to refer to the smallest features that can be reliably manufactured, as was in the case of planar transistors, but to denote a new generation of process technology and devices that offer better performance and efficiency than their predecessors. This technique, known as monolithic 3D integration, involves the fabrication of thinner functional tiers separated by interlayer dielectrics and interconnected via monolithic inter-tier vias12. Several predictions and analyses already highlight the opportunities and advantages of monolithic 3D integration, including increased interconnect density, reduced electrical parasitic capacitance, enhanced energy efficiency and better performance13,14,15,16. The future technologies will integrate novel 3D IC packaging and integration solutions with monolithically 3D-integrated individual chips.

It is interesting to note that, despite its conception in the 1980s17,18,19, initial research on 3D integration was not actively pursued. This lack of interest was due to the then-prevalent trend of downsizing individual silicon-based transistor dimensions — a process made feasible through advances in materials science, electronics and nanofabrication. Consequently, transistor device dimensions shrank dramatically, transitioning from the micrometre regime to the realm of tens of nanometres. This period marked the introduction of high-κ dielectrics and strained silicon technology, as well as a shift from the classical planar field-effect transistor (FET) structure to newly emerging architectures. These include non-planar fin-shaped FETs (finFETs), gate-all-around (GAA) FETs (also known as nanosheet FETs, ribbon FETs, and multi-bridge channel FETs), and the potentially forthcoming forksheet FETs and complementary-FETs20,21,22. This evolution, which began in 1959, is depicted in Fig. 1a. However, it is challenging to scale transistors down further by reducing the thicknesses of semiconductor channels to less than 3 nm, because of inherent issues in silicon and other bulk semiconductors, such as increased charge carrier scattering at the semiconductor–insulator interface and subsequent mobility degradation23,24. Along these lines, among other contenders such as carbon nanotubes and nanowires, ultrathin 2D semiconductors emerge as promising materials to facilitate the continued miniaturization of transistor dimensions25.

Fig. 1: Evolution of silicon technology and 2D electronics.
figure 1

a, Evolution of silicon-based transistor technology highlighting key milestones achieved since 1959. b, Evolution of 2D electronics: material synthesis and device performance. Although the first 2D material — graphene — was discovered in 2004, it was not until 2011 that the first transistor based on a 2D semiconductor was demonstrated. Since then, the performance of 2D-based field-effect transistors (FETs) has substantially improved, surpassing existing silicon technology in some instances. MOS, metal–oxide–semiconductor; CMOS, complementary metal–oxide–semiconductor; MoS2, molybdenum disulphide; MoSe2, molybdenum diselenide; MOCVD, metal–organic chemical vapour deposition; WS2, tungsten disulphide; RC, contact resistance; κ, the dielectric constant; TMD, transition-metal dichalcogenides. Data are taken from refs. 29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,140,207.

From a materials perspective, 2D semiconductors, particularly transition-metal dichalcogenides (TMDs), have drawn tremendous attention in the past decade with demonstrations of high-quality wafer-scale synthesis, high-performance FETs, in-sensor and in-memory computing, optical, biological and chemical sensors, scaled FETs, and so on26,27,28. The progression in the development of growth technologies29,30,31,32,33,34 for 2D TMDs and the performance of their electronic devices35,36,37,38,39,40,41,42,43 is illustrated in Fig. 1b. Apart from that, 2D materials also have applications in twistronics, spintronics, straintronics, valleytronics and flexible electronics44,45,46,47,48. Hence, as shown in Fig. 2, 3D integration with 2D electronics not only presents alternative pathways for scaling individual devices in line with the ‘more Moore’ approach (continued scaling in accordance with Moore’s law) but also provides diverse functionalities that can be leveraged to co-design and incorporate non-computational devices within the same platform, facilitating the realization of ‘more than Moore’ technologies49. In addition, theoretical studies have predicted that incorporating 2D electronics into monolithically integrated 3D chips can increase the integration density50.

Fig. 2: 3D Integration of 2D electronics.
figure 2

a, Schematic of 3D integration of 2D electronics: additional functionalities such as sensing and storage with logic can be enabled in a 3D integrated chip based on 2D materials. b, ‘More Moore’. 2D field-effect transistors (FETs) can provide scaling benefits when introduced in gate-all-around FETs (GAAFETs) (right) and stacked FETs (also known as complementary-FETs) (left). c, ‘More than Moore’. 2D FETs can also facilitate the integration of non-computational devices within 3D architectures for applications in chemical/bio sensing, optoelectronics and memory. Part a reproduced from ref. 207, Springer Nature Limited.

Here, we review the progress towards 3D integration of 2D electronics and its prospects and challenges. The review begins with a section on progress and challenges towards very-large-scale integration (VLSI) of 2D electronics followed by a summary of various 3D IC demonstrations that use 2D materials. Finally, we conclude this Review with a section on comprehensive device design considerations and the associated challenges.

Towards very-large-scale integration of 2D electronics

Here, we succinctly highlight the advances in various facets of 2D electronics, while simultaneously addressing the immediate challenges that need to be met. Overcoming these obstacles is imperative for the eventual realization of industrial-scale production of 2D-based 3D ICs.

Material synthesis

Growth techniques for 2D materials have evolved considerably from mechanical exfoliation since the discovery of graphene. Initially, wafer-scale synthesis efforts included the chemical vapour deposition (CVD) of MoS2 on SiO2 substrates, achieving millimetre-scale coverage51,52. By 2015, MoS2 and WS2 synthesis expanded to 4-inch SiO2/Si wafers using metal–organic chemical vapour deposition (MOCVD). Simultaneously, the synthesis of MoS2 on other substrates, such as Al2O3, HfO2 and SiN, was also reported29. In 2017, IMEC used atomic layer deposition (ALD) or plasma-enhanced CVD to fabricate back-end-of-line (BEOL) compatible WS2 transistors on 300-mm SiO2/Si wafers53. In 2018, ~6-inch batch production of MoS2 on soda-lime glass via a face-to-face metal-precursor feeding route in a CVD process was demonstrated54. In 2021, Intel identified CVD growth from pre-patterned seeds, and MOCVD as leading techniques for synthesizing MoS2, WSe2, MoSe2, and WS2 on 300-mm SiO2/Si wafers, which provides both transfer and direct deposition options31. Concurrently, epitaxial growth of 2D TMDs on sapphire substrates (via CVD or MOCVD) made strides owing to the high quality and uniformity of the synthesized 2D crystals55,56. In addition, step engineering of growth substrates and adjustable growth conditions could control the nucleation and growth direction, making it possible to obtain wafer-scale uniform single-crystal films of MoS2 (refs. 57,58), WS2 (ref. 59) and WSe2 (ref. 60). Changing growth conditions can alter the nucleation of 2D materials on step edges, so that it transitions from occurring predominantly at the top edge to the bottom edge of the step, thus shifting the preferred domain orientation. A recent advance has been made in the uniform nucleation and epitaxial growth of bilayer MoS2, achieving ON-state FET performance that aligns with the International Roadmap for Devices and Systems 2028 objectives32. In 2023, non-epitaxial single crystal 2D growth by geometric confinement was demonstrated33. Direct growth of MoS2 on 200-mm silicon complementary metal–oxide–semiconductor (CMOS) circuits at 300 °C (ref. 34), and on flexible substrates such as polymers and ultrathin glasses at 150 °C (ref. 61), aligns well with 3D integration needs because of their low thermal budgets. However, achieving epitaxial quality across all 3D stack tiers is essential for industrialization. Sequential monolithic 3D integration based on the transfer of 2D materials from growth substrates to target chips or wafers could be another option. We note that the underlying substrate properties will be different for the fabrication of the second tier of devices in comparison to the first tier because the fabrication steps and conditions will have to be adjusted in order not to cause any damage to the already fabricated tier-one devices. (Here, the word tier is used to refer to different levels of device). In contrast, the general high temperature and substrate requirements for epitaxial synthesis makes the transfer process promising for 3D stacking. Regardless, controlling film thickness and uniformity, and minimizing defects and contamination during synthesis or transfer, are vital for optimizing the yield and variability of 2D FETs. Furthermore, surface treatments of the 2D channels31,62 during tier-two fabrication might affect bottom-tier device performance, thus necessitating comprehensive studies on both the 2D-material–contact interfaces and the interlayer-dielectric–2D-material–gate-dielectric interfaces (depending on the device architecture; 2D material will not have an interface with the interlayer dielectric in a gate-all-around architecture, but can form an interface in the case of planar devices) of tier-one devices before and after fabrication of tier-two devices. Although both direct deposition and transfer approaches show potential, the ideal technique for 3D integration of 2D FETs remains to be determined.

Transfer process in 2D electronics

Following epitaxial growth, 2D materials can be transferred from high-temperature growth substrates to desired target substrates (with pre-fabricated back-gate dielectric stack or substrates for top-gate processing) using (1) polymer-assisted wet transfer methods, (2) polymer-free transfer methods or (3) deterministic dry transfer methods63. We note that the use of polymers and associated cleaning steps often induces undesirable defects in the 2D films. From an industrial perspective, the ideal technique must enable high-throughput wafer-scale 2D transfers with high yield and clean interfaces. Some of the earlier notable attempts involved transfer of 5-cm-diameter 2D-material wafers64,65. Water-based etching-free 6-inch MoS2 transfer using a ethylene vinyl acetate/polyethylene terephthalate stack was demonstrated in 2018 (ref. 54). Similarly, IMEC has demonstrated 300-mm transfer of WS2 using temporary wafer-to-wafer bonding and a laser debonding technique38,66. In 2022, TSMC utilized evaporated Bi as a gentle adhesive layer to perform 2-inch WS2 dry transfer67. There also exist Au-assisted 2D transfer processes, as shown previously57,68. Recently, IMEC developed the collective die-to-wafer (CoD2W) technique and demonstrated a two-step residue-free transfer of both MoS2 (epitaxial growth on 2-inch sapphire using water intercalation) and WS2 (grown on SiO2 with completely dry debonding) to 300-mm target wafers using adhesive-coated glass carriers69. From an automation perspective, a notable demonstration involved 100 µm × 100 µm 2D transfer with high speed and precise angle control using a robotic assembly70. In addition, 2D FETs suffer from the phenomenon of Fermi-level pinning71, which causes the Schottky barrier height at the metal–semiconductor junction to be independent of the metal work function, leading to less control when engineering the contact resistance. Some studies suggest that Fermi-level pinning can be somewhat alleviated by minimizing the defects in the 2D channel during contact deposition72,73,74. As a result, the technique of transferring pre-assembled arrays of metal contacts onto the 2D semiconductor is becoming a promising alternative for contact engineering74,75,76,77,78. Similarly, there have been various demonstrations of dielectric transfer79,80,81. These demonstrations, including those from industry, point towards the potential of the transfer process as a scalable integration step in 2D electronics.

To effectively execute a transfer strategy for 2D electronics, several crucial metrics must be considered. These include the ability to transfer large-area films at the wafer level while ensuring the structural integrity of the transferred films. Achieving scalability and automation is imperative for industry acceptance. Additionally, the interface of the transferred 2D material and the target substrate should not contain defects or contaminants. Uniformity and reproducibility across the entire wafer, minimizing device-to-device variation, are critical for reliable outcomes. But we note that, even though transfer techniques show promise, an ideal scenario would involve high-quality growth of 2D materials at BEOL-compatible temperatures.

Threshold voltage engineering

Managing the threshold voltage (VTH) of a FET allows control over its ON-state. This critical parameter depends on factors such as the gate dielectric, the work function of the gate metal, and the unintentional or intrinsic doping within the 2D material. In the realm of digital circuits designed for low power consumption, minimizing the VTH is paramount. With increasing chip density, there has been a corresponding rise in power consumption, resulting in undesirable levels of heat generation. In this context, maintaining a low operating voltage is crucial, which requires precise control over VTH for both n-type and p-type FETs. Furthermore, CMOS circuits demonstrate optimal performance only when the VTH for both n-type and p-type FETs are carefully calibrated. Suboptimal VTH values can substantially affect signal propagation within CMOS circuits. Overall, VTH engineering is vital to meet the specific requirements of various electronic applications. In Si-based CMOS technology, doping in the semiconductor channel and altering the work function of the gate electrode material are used for finely tuning VTH. However, comparable progress in VTH engineering of 2D electronics is still limited. Techniques such as substitutional doping and surface charge-transfer doping (SCTD) can be used to control the VTH of a 2D FET. Substitutional doping involves the substitution of cationic and anionic elements with foreign atoms that have similar radii82. For p-type doping, cationic elements like niobium (Nb), tantalum (Ta) and vanadium (V) can be used, while rhenium (Re), hafnium (Hf), and zirconium (Zr) are utilized for n-type doping83,84,85,86,87. Despite demonstrations of devices utilizing doped TMDs88,89,90,91, achieving a uniform impurity density and precise control at large scale, while using methods compatible with state-of-the-art Si CMOS process lines, still presents a substantial challenge. The VTH in p-type WSe2 FETs can be modulated by adjusting the percentage of V atom doping85. This modulation was achieved by precisely controlling the partial pressure of precursors during MOCVD growth. Another challenge with substitutional doping of 2D materials arises from the fact that the ionization energy of dopants is substantially higher (by an order of magnitude) than their ionization energies in bulk semiconductors. This discrepancy is attributed to the quantum confinement effects observed in 2D materials. Consequently, dopant concentrations exceeding one atomic per cent, which far surpass the levels used in traditional doping, are necessary to alter the transport properties of 2D TMDs. Such high doping concentrations can degrade the field-effect mobility of the devices owing to an increase in scattering centres. The exact doping concentration required for mobility degradation cannot be stated because it is influenced by various factors, such as the nature of the dopant atom (atomic mass) and the characteristics of the 2D film92. Limited research has been conducted into the impact of doping concentration on mobility degradation, making it a prospective area for future investigation. This issue could be mitigated if the dopant were to create shallower donor levels, allowing for easier carrier activation. In this regard, Re is a transition metal known to form shallow donor levels with MoS2 (refs. 93,94). MoS2 monolayers can be n-doped by substituting Mo with Re atoms, achieving controllable concentrations down to 500 parts per million using MOCVD87. Their findings demonstrated that an increase in Re concentration led to a reduction in the number of sulfur (S) vacancies, resulting in a shift in VTH and subsequently enhanced device performance. The higher free energy of formation of S vacancies as a result of Re doping has been claimed to be the reason for fewer S vacancies. This substitutional approach can also be extended to anionic replacement95,96,97.

Another doping approach for modulating VTH of devices is SCTD. For the effective implementation of the SCTD approach, it is essential to meticulously design the gate stack. This design should ensure three key aspects: (1) the equivalent oxide thickness (EOT) must remain unaffected, (2) the gate control should be maintained, and (3) the channel material must not suffer any damage. In SCTD, dopant atoms are attached to the 2D material through either a chemical bond or a physical interaction, resulting in a charge-transfer process. The direction of charge transfer is determined by the Fermi-level difference between the dopant and the host materials, dictating whether the adsorbed dopant functions as an acceptor or a donor. Unlike substitutional doping, SCTD does not introduce any lattice disorders, because dopants are positioned outside the electrical carrier pathways. As a result, SCTD in general enables the retention of higher electrical mobility in the 2D materials. SCTD has been successfully demonstrated in various TMDs, allowing for both n- and p-type doping with different degrees of effectiveness98,99.

Additionally, ozone or oxygen plasma treatment can be applied to transform the top layer of TMDs into their corresponding sub-stoichiometric oxides, resulting in substantial p-type doping in the layers below100. The previous study shows that converting atomically thin WSe2 to WOx led to strong hole-doping owing to electron transfer from the underlying WSe2 to the surface WOx (ref. 101). Doping can also be induced by depositing a sub-stoichiometric insulator on top of the 2D material. This doping can occur through two processes. The first involves the transfer of charge due to trap states at the semiconductor/oxide interface or in the oxide near the interface (such as border traps). The second process involves doping the 2D material via the transfer of electrons or holes from states that do not overlap with the energy gap of the 2D semiconductor. The challenge lies in achieving doping through this latter process, given that it does not degrade the subthreshold slope and mobility of the device. It has been demonstrated that an improvement in the device performance can be achieved, along with a large VTH shift of around 20 V, by depositing aluminium oxide102. Other oxides, like amorphous titanium suboxide103, molybdenum trioxide100,101,104 and silicon nitride105 have also exhibited similar behaviour. These avenues hold promise for addressing the VTH engineering challenges in both n- and p-type 2D FETs, a crucial step towards realizing 2D CMOS circuits. Studies have also explored tuning the threshold voltage by incorporating an interfacial layer in the gate dielectric, with a predominant focus on silicon. As a result, a shift in flat band voltage can be obtained by introducing titanium (Ti) and Hf in a metal/high-κ gate stack106. Even though there is a scarcity of research on 2D materials concerning the dipoles originating from the gate dielectric, research into dipoles induced by organic polymers, capable of altering the threshold voltage in 2D materials, has been conducted92,107,108. In another study, gadolinium aluminate was used in the dielectric stack to gain control over the threshold voltage109.

In addition to all this, it is also important to note that device-to-device variation can stem from defects in the as-grown 2D material or at the interface between the 2D material and the dielectric. Acceptable device-to-device variability is thus a crucial milestone for 2D electronics which is yet to be achieved110. Thus, threshold voltage engineering techniques must be developed hand-in-hand with interface engineering and a focus towards reducing device-to-device variation on the large scale.

Yield, variability and dielectric integration

In addition to VTH engineering, achieving high device yield and minimizing device-to-device variability are other crucial prerequisites when designing and demonstrating large-scale CMOS circuits. While device yield affects the effective design of integrated circuits, such as the footprint, uniformity in device performance is essential for the proper operation of CMOS circuits (achieving correct voltage levels).

Transferring synthesized 2D materials poses challenges owing to their atomically thin and exceedingly delicate structure. Moreover, the capillary forces that arise when the film is removed from the solution bath can cause the material to wrinkle, fold and crack. Conversely, direct growth of 2D materials on substrates suitable for commercial applications is often constrained by the requirement for high growth temperatures, the use of chemically reactive precursors and the need for epitaxial alignment. Such elevated growth temperatures can cause the deterioration of the underlying substrate, thereby adversely affecting device performance and reliability111,112,113.

To improve the yield and reliability of 2D FETs, in addition to fine-tuning or eliminating the transfer process, there is a need for comprehensive optimization in both the growth of 2D materials and process integration. The growth of 2D materials must be a very precise and controlled process in order to control the quantity of vacancies and defects, with the ultimate goal of ensuring that the as-grown material exhibits minimal vacancies and defects. A uniform crystalline film is also essential to achieve good yield and better reliability. The number and distribution of grain boundaries can play a part in determining both the performance and uniformity of devices. Devices that are smaller than the average grain size tend to be less affected by these boundaries, whereas larger devices are more susceptible to their influence. In particular, a device located directly on a grain boundary can experience pronounced effects. The variability in device characteristics, especially when comparing devices with different numbers of grain boundaries, is an important consideration. However, this variability can be mitigated by increasing the grain size and improving the growth process, thereby making the material more uniform. While addressing the challenges posed by grain boundaries is an ongoing area of research, it is worth noting that they might not necessarily be a limiting factor in device variation. This is especially true given the sizes of domain typically achieved in current 2D-material growth techniques. Additionally, on a circuit level, the tolerance for device-level variability tends to be higher. Circuits can often accommodate a certain degree of variation in individual components without notable loss of overall functionality. This inherent resilience could mean that grain boundaries, although a critical factor in device variation, might not be a critical obstacle. Therefore, although grain boundaries can contribute to device variability, their eefect might be less critical at the circuit level. Continued research and development in material growth and processing techniques will further clarify their role and potential ways to mitigate their effects on device performance. Therefore, grain boundaries are a crucial factor to consider, but they do not inherently preclude the effective use of 2D materials in scaled devices.

Additionally, mitigating device variability involves fine-tuning contact formation, optimizing the integration of gate dielectrics and incorporating effective post-fabrication device treatments or annealing steps. In this context, it is worth noting a study110 in which the effect of imperfections of individual FETs on 2D-based electronic circuits was thoroughly examined. The authors emphasize the importance of electrically active traps that can arise from defects at various points in the FET structure, such as the channel, the dielectric and the interface between the channel and the dielectric. These traps can introduce variability in VTH of individual devices, underscoring the need for meticulous optimization. Thus, the advances towards the development of high-density 3D CMOS circuits built upon 2D FETs must also prioritize enhancing yield through the optimization of synthesis, transfer and fabrication processes. Equally crucial is the selection of a compatible 2D-material–dielectric combination that minimizes device-to-device variability. Even though device variability was not studied, there has recently been some work on incorporating crystalline dielectrics such as CaF2 (ref. 114) and SrTiO3 (ref. 79) with low EOT in 2D electronics.

In addition, the integration of ultrathin high-κ dielectrics with 2D materials is a crucial component, particularly in GAA device architectures. To achieve successful integration of scaled dielectrics, two critical factors are essential: low leakage currents (less than 10–2 A cm–2) and high dielectric strength (greater than 10 MV cm–1)115,116. The attainment of these characteristics is closely tied to having a high dielectric constant and a large bandgap. Noteworthy materials that meet these specifications include HfO2, with a dielectric constant of approximately 23, and CaF2, with a bandgap of around 12 eV. It is important to highlight that within this context, the physical thickness of the dielectric layer is not as vital as the EOT. The primary objective is to minimize the EOT to less than 1 nm. Substantial strides have been made towards this objective, such as the achievement of reducing HfO2 thickness to attain an EOT of less than 1 nm, alongside an impressive ON-state current (ION) performance of approximately 420 µA µm–1 in a dual-gated MoS2 MOSFET configuration. This approach incorporated an interfacial layer of gadolinium aluminate within the dielectric stack, thereby enabling effective VTH control and enhancing carrier transport properties109. Additionally, the capability to achieve an EOT of 1 nm for graphene, MoS2, and WSe2 devices has been demonstrated, attributed to the use of an ultrathin (~0.3 nm) layer of perylene-tetracarboxylic dianhydride (PTCDA) molecular crystals as a seeding layer. CaF2 insulators could also enable scaling down to less than 1 nm EOT (with a physical thickness of 2 nm), thereby achieving not only low leakage currents but also competitive device performance, including a subthreshold swing down to 90 mV dec–1 (ref. 117). These advances underscore the importance of novel approaches in the pursuit of scaled dielectrics with enhanced electrical properties. Apart from that, GAA deposition techniques for 2D materials have been demonstrated, but further exploration into integration challenges such as the damage to the 2D channels during gate-stack or contact formation is necessary118. GAA single-layer MoS2 devices, for instance, have shown an ION of 410 µA µm–1 and a subthreshold swing of 220 mV dec–1, indicating the viability of GAA architectures for 2D materials43. However, the variety of dielectric stacks and gate metals used in various studies makes direct comparison of the findings challenging. Therefore, a new parameter, the projected threshold voltage variation (SσVTH), has been introduced to facilitate comparisons across various studies on 2D materials and with the silicon industry119. As a result, a relatively low SσVTHvalue of 33 mV was obtained, compared with those of state-of-the-art ultra-thin-body silicon-on-insulator and silicon finFETs, which were 13 and 20 mV, respectively120,121. Addressing the concerns discussed in this section is pivotal for further improvements in reducing threshold voltage variation.

Device performance

Despite various advances, the performance of 2D FETs is still hindered by contact limitations. The primary issue revolves around achieving contacts that demonstrate ohmic behaviour. In contrast to silicon-based devices, where low-resistance ohmic contacts are obtained through precise doping via ion implantation of the underlying silicon beneath the metal, replicating such results in 2D materials is hindered by their atomically thin nature. Additionally, the process of engineering contacts for 2D materials is further complicated by phenomena such as Fermi level pinning71. Ongoing research in the field of 2D materials has recently led to breakthroughs demonstrating ultralow contact resistance in these materials, surpassing the capabilities of traditional silicon-based CMOS technologies and meeting the targets set for 2028 by the International Roadmap for Devices and Systems. A notable achievement includes the realization of ultralow contact resistance of 123 Ω µm using bismuth (Bi) contacts39. However, it is not practical to use Bi owing to its low melting point (below 300 °C), prompting a shift towards antimony (Sb) as a more viable contact metal for MoS2 thanks to its higher melting point (above 600 °C). This switch has enabled the demonstration of ultralow contact resistance of 42 Ω µm (ref. 40) and reported currents exceeding 1 mA µm–1. Further progress has been seen in achieving the on-state current (ION) of 1.27 mA µm–1 (at a drain-to-source voltage of 2.5 V) in short-channel (50 nm) FETs based on bilayer MoS2.

In another report, the FETs made from mechanically exfoliated InSe flakes showed ballistic transport achieved by using a phase-transition method induced by yttrium doping122. The channel length could be scaled down to 10 nm while attaining a contact resistance as low as 62 Ω µm. Although these results hold promise, further exploration is required for reproducibly achieving such high performance on a larger scale. Furthermore, the successful integration of large-scale 2D CMOS requires comparable performance from both n-FETs and p-FETs. While substantial progress has been made in achieving high ON currents for n-type 2D FETs, replicating these successes for p-type counterparts has presented remarkable challenges as given below.

p-type 2D FETs

Two major obstacles towards p-type 2D FETs include Fermi-level pinning and substrate-induced electron doping by charge transfer123. The Fermi-level pinning is generally believed to be caused by (1) defects in the metal–semiconductor interface (which could be intrinsic defects in the 2D semiconductor, defects generated with the deposition process, adsorbates or other contaminants), (2) strain at the metal–semiconductor interface causing bandgap changes, or (3) reduction of the metal work function due to the formation of interface dipoles caused by the electron density redistribution at the metal–semiconductor junction. In addition to Fermi-level pinning, substrate induced charge transfer electron doping of 2D semiconductors is also observed, which can be caused by impurities or atomic vacancies in the dielectrics123. In most cases, the above-mentioned effects are unfavourable for achieving hole transport and thus, ‘purely’ p-type 2D FETs (without any n-branch). However, some recently published research aimed to achieve p-type 2D FETs with either substitutional doping (mentioned in the section ‘Threshold voltage engineering’) or contact engineering strategies. In terms of contact engineering, transferring high-work-function metals in van der Waals metal–semiconductor junctions has helped to achieve better hole transport74,76,78. Inserting a buffer material such as In or Se between the semiconductor and contact metal was also used to achieve clean and less-damaged contacts73,124. Another route, distinct from the above-mentioned techniques, is the treatment of WSe2 after growth to achieve hole transport. For example, oxygen plasma treatment on transferred WSe2 flakes125, immersion of WSe2 in an aqueous solution of 4-nitrobenzenediazonium tetrafluoroborate (4-NBD)126 and exposing WSe2 devices to nitric oxide gas flow62, have all helped to achieve p-type 2D FETs. In another distinct approach, VSe2 was grown on WSe2, followed by the formation of cracks to achieve small channel p-type FETs with atomically clean interfaces127. Recently, another demonstration involved p-type electrical contacts for 2D TMDs such as (exfoliated) WSe2 fabricated with industry-compatible electron-beam evaporation of high-work-function metals such as Pd and Pt72. Though promising, more such efforts are required in order to improve p-FETs and reach the performance levels of 2D n-FETs. Only then, can we achieve 2D CMOS, which can evolve to VLSI of 3D CMOS with 2D electronics.

The above discussion has provided insights into advances in 2D semiconductor research, encompassing contributions from both academic and corporate research environments. Leading semiconductor giants such as Intel and TSMC have notably incorporated 2D materials into their roadmaps. Corporate research initiatives in the field of 2D semiconductors are outlined in Box 1, offering an overview of some of their key findings and accomplishments to date (including some reports that have been discussed above). Recently, Intel also published an article on their perspective on 2D transistors including discussions on challenges and strategies associated with deposition of 2D materials, formation of stacked 2D nanoribbon channels, doping, gate-dielectric/contact formation and contact resistance118.

Researchers in the 2D electronics field must establish realistic objectives. For silicon-based technologies, these targets are typically provided by the International Roadmap for Devices and Systems. In the realm of 2D electronics, a comprehensive set of targets has been identified, outlining intermediate, critical and long-term goals for 2D transistors. These targets are crucial for the transition from laboratory to real-world applications128. Specifically, the critical targets for high-performance ION, low-performance ION, mobility (µ), external resistance and subthreshold swing are 1.5 mA µm–1, 1 mA µm–1, 500 cm2 V–1 s–1, 200 Ω µm and 65 mV dec–1, respectively. These parameters are essential for achieving VLSI of 2D electronics.

3D integration of 2D electronics

3D integration of 2D materials has various applications, as depicted in Fig. 3. These applications can fall into two categories: (1) stacking 2D materials to maximize area utilization and facilitate scaling, and (2) integrating 2D materials or devices on top of silicon-based logic or memory devices. The following sections provide a summary of these topics.

Fig. 3: Applications of 3D integration of 2D electronics.
figure 3

a, Integration of 2D materials with silicon logic for optoelectronics. b, Monolithic 3D complementary metal–oxide–semiconductor (CMOS) with 2D field-effect transistors (FETs). c, Incorporation of sensing and memory functionalities with logic, all based on 2D materials. d, 2D-based multi-bridge channel FETs. e, 2D-based complementary-FETs. f, Integration of 2D materials and memory devices. C1 and C2 denote MoS2-based transistors in first and second levels of 1-transistor/1-resistor memory cells, respectively, and C3 is used to denote the h-BN-based resistive random-access memory (RRAM) in the second level. g, Direct growth of 2D materials on silicon CMOS wafers for 2D-silicon heterogeneous 3D integration. h-BN, hexagonal boron nitride; BEOL, back-end-of-line; MOCVD, metal–organic chemical vapour deposition; ZrO2, zirconium dioxide. Part a reproduced from ref. 142, Springer Nature Limited. Part b reproduced from refs. 130,131, Wiley. Part c reproduced from ref. 133, Wiley. Part d adapted with permission from ref. 136, Wiley. Part e reproduced from ref. 138, Wiley. Part f reproduced from ref. 143, IEEE. Part g reproduced from ref. 34, Springer Nature Limited.

Stacked 2D FETs

The first demonstration of 3D integrated electronics utilizing stacked 2D materials was reported in 2012 (ref. 129). This work involved the mechanically exfoliated n-type MoS2 on top of a p-type Bi2Sr2Co2O8 — a layered transition-metal oxide that can be exfoliated — to create a 3D inverter. The full stack consisted of graphene (for the supply voltage node), Bi2Sr2Co2O8 (p-channel), graphene again (for the output node), MoS2 (n-channel) and Ti/Au (the ground) layered on a Si/SiNx substrate129. By 2015, advances had been made in the sequential fabrication of MoS2 FETs, starting with the growth of the first MoS2 layer on a SiO2/Si wafer. This process included device fabrication at the first tier, followed by SiO2 encapsulation, and was repeated for a second-tier device. However, these devices shared a common global back-gate, and the focus was largely on the MOCVD growth of 2D materials on 4-inch SiO2/Si wafers, rather than on 3D integration29.

Substantial progress in 3D integration was reported in 2016 (ref. 130) (Fig. 3b), showcasing the use of mechanically exfoliated 3–7-nm-thick MoS2 and WSe2 flakes as n- and p-type channel materials, respectively, with 20-nm-thick ZrO2 deposited via atomic layer deposition as the gate dielectric. The corresponding NMOS and PMOS devices had gate length/width dimensions of 2 µm/3.3 µm and 2 µm/5.5 µm, respectively. This work resulted in the fabrication of digital (inverter, NAND and NOR) and analog (amplifiers and signal mixers) CMOS circuits, marking a notable achievement in the field. Concurrently, the silicon industry’s exploration of nanosheet technology for GAAFETs paralleled proposals for 3D stacking of 2D FETs, aimed at increasing drive currents (535 µA µm–1 ON-state currents for a channel length of 370 nm at a VDS of 4.5 V)131. With a channel length/width of around 370 nm/2 μm, they were able to increase the drive current by an order of two with the dual-channel FETs.

In 2019, evaporated 8-nm-thick Te thin films were used to fabricate and stack p-type FETs to achieve a PMOS logic 3D inverter132. In addition, device statistics from around 60 individual p-type FETs were also obtained. This period also saw 2D materials being used to integrate sensing or memory functions into 3D ICs. A layer-by-layer stacking approach enabled the demonstration of devices across three tiers (Fig. 3c), utilizing exfoliated few-layer graphene and 45–47-nm-thick hexagonal boron nitride (h-BN) for gate/contact electrodes and dielectrics, respectively, with transferred CVD-grown MoS2 serving as the semiconducting channel133. Consequently, the first, second and third tiers comprised three two-terminal memories, three in-plane inverters and NAND gates, and three individual optical sensing FETs, respectively.

Despite these advances, challenges such as the reliance on mechanical exfoliation and the use of h-BN as the gate dielectric were limiting factors for scaling134. Nonetheless, the connection of three vertically stacked FETs demonstrated an increase in current densities (ION = 54 µA µm–1 at VDS = 1 V for a 3-µm channel length), because this design increases the effective width while maintaining the same active device area of a single FET. Further progress in 2021 included the monolithic fabrication of 3D inverters using vertically stacked n-type MoS2 and p-type WSe2 FETs, alongside the use of chemical doping for threshold voltage engineering135. Exploration continued with the development of MoS2-based multi-bridge channel FETs136 (Fig. 3d) and further demonstrations of 3D-integrated inverter, NAND and NOR circuits using CVD-grown MoS2 and MoTe2 for n-FETs and p-FETs, respectively137. In these devices, HfO2 was used as the gate dielectric and the channel length was relatively large at 10–20 µm. The same year, another demonstration involved the fabrication of 22 complementary-FET devices with p-type WSe2 FETs stacked on top of n-type MoS2 FETs138 (Fig. 3e). CVD was used to grow both 2D materials while HfO2 deposited by atomic layer deposition was used as the gate dielectric. The channel length and width were both 5 µm. A similar demonstration involved the fabrication of 3D inverters using p-type MoTe2 and n-type MoS2 (ref. 139).

The most recent notable advance in 3D-integrated 2D electronics involves the demonstration of (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 FETs in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length 45 nm) in each tier140.

Integrating 2D with logic or memory

2D materials are being explored not only for their potential in scaling FETs but also for incorporation into BEOL transistors and applications. Early developments along this route involved the use of 2D materials for optoelectronic applications. In 2016, researchers successfully transferred CVD-grown MoS2 onto interlayer-dielectric-encapsulated silicon-based logic or memory tiers on a silicon wafer141. The top tier consisted of a 5 × 5 phototransistor array, based on CVD-grown MoS2, while the bottom tier comprised 6-transistor static random-access memory (6T SRAMs) using poly-silicon nanowire FETs. A transparent conducting oxide served as the top-gate metal, facilitating the light–matter interaction in 2D materials. This work also introduced the idea of using other 2D TMDs with different bandgaps for wavelength-dependent optical sensing.

The substantial potential for monolithic 3D integration of 2D materials with silicon CMOS technology was further demonstrated in 2017 with the development of a 388 × 288-pixel broadband image sensor142 (Fig. 3a). This sensor was manufactured by transferring CVD-grown graphene onto a pre-fabricated silicon CMOS die, complete with vertical interconnects and read-out circuitry. Lead sulfide colloidal quantum dots were deposited onto the patterned graphene pixels, serving as the light absorption layer. The photodetection mechanism in the device arises from the photogating effect and charge transfer from the quantum dots to the graphene layer, which enables ultrahigh gain and photoresponsivity. The incorporation of graphene remarkably improved the dynamic range, responsivity and broadband detection capabilities (300–2,000 nm), showcasing the benefits of monolithic 3D integration with 2D materials.

Monolithic integration has also been applied to embed memory functionalities into 2D FETs. In 2018, a team demonstrated a two-level stacked 2 × 2 one-transistor, one-resistor (1T1R) array combining local back-gated MoS2 transistors with h-BN-based resistive random-access memory (RRAM) devices143 (Fig. 3f). Despite the need for additional planarization steps owing to surface roughness, the fabrication flow emphasized the feasibility of integrating memory devices with 2D FETs in a 3D architecture.

In 2022, another team transferred CVD-grown MoS2 onto HfO2-encapsulated p-type silicon FETs showcasing 3D inverter and two-input NAND and NOR circuits144. The channel lengths and widths of both n-FETs and p-FETs were 10 µm and 16 µm, respectively. A similar effort led to the monolithic integration of a 3D CMOS inverter, achieved by fabricating top-gated 2D FETs based on CVD-grown MoS2 on top of silicon finFETs145. These advancements highlight ongoing improvements in the transfer process and the development of low-temperature wafer-scale growth techniques for 2D materials. A notable example includes the use of a MOCVD reactor that separates the low-temperature growth region (where the target substrate is placed) from the high-temperature chalcogenide-precursor-decomposition region. This setup enabled the direct growth of MoS2 on a 200-mm silicon CMOS wafer at temperatures below 300 °C, meeting BEOL temperature requirements and facilitating the heterogeneous integration of a MoS2–silicon SRAM cell)34 (Fig. 3g).

Similarly, 2D h-BN (~6 nm) was transferred onto pre-fabricated silicon–CMOS microchip to integrate memristors with silicon CMOS transistors, paving the way for in-memory computing with one-transistor, one-memristor (1T1M) cells146. Beyond electronic applications, 2D materials are also being widely explored for their potential in photonic applications within a 3D-integrated architecture147. The most recent notable advance includes the demonstration of an AI-processing hardware using six layers of transistor and memristor arrays based on MoS2, WSe2 and h-BN140. These authors utilized the capability to peel off a flexible substrate from a rigid carrier substrate after device fabrication and stack it on the target substrate. The work is an important milestone in the path towards enabling next-generation wearable electronics.

Design considerations and challenges

Once reliable 2D-based circuits can be reproducibly manufactured on the large scale, the subsequent objective is to expand this technology into 3D integration, which presents unique challenges that demand dedicated research efforts to address. In this section, we provide a comprehensive evaluation of various design considerations that are critical for the development of 2D-based monolithic 3D ICs. We note that design considerations for electronic devices vary substantially, depending on the desired functionalities the final product is intended to perform. When it comes to heterogeneous monolithic 3D integration — combining different materials, devices and functionalities within a single chip leads to an increase in complexity. Hence, crafting chips for specific tasks requires dedicated designs and specialized process flows. The overarching goals are to improve performance, power efficiency and integration density, to minimize size and costs, to optimize resource allocation and to increase signal speed. We start by examining design considerations related to materials, devices and fabrication techniques, then move to surface planarization, thermal management and reducing electrostatic coupling, and finally conclude with a discussion of the general architectural design principles for 3D ICs.

Materials, devices and fabrication techniques

The selection of devices and functional blocks for a 3D chip is determined by the desired functionalities, which include n- and p-type 2D FETs, memory devices and sensors for optical, biological and chemical applications, as well as Si-based circuits, among others. Each type of device has its own set of fabrication needs and limitations, which affect the choice of materials and technologies used for creating connections between layers (inter-tier vias), insulating layers between tiers (inter-tier dielectrics), thermal dissipation and electrical interference screening layers. In addition, choosing materials for these different functionalities also requires consideration of their thermal properties, such as the coefficient of thermal expansion and thermal conductivity, as well as their compatibility with the fabrication process.

After the selection of materials for the desired devices, it is crucial to address the fabrication complexities associated with their integration into a 3D chip. For instance, in a Si-based 3D prototype, low-temperature molecular bonding of silicon-on-insulator was used to minimize performance degradation in the bottom tiers148. It is essential to evaluate the effect of process variations during the sequential fabrication of top tiers on the performance of bottom-tier devices, particularly in heterogeneous 3D integration. Key issues to consider include the presence of voids at interfaces149, the quality of inter-tier dielectrics, the occurrence of resistive shorts or opens in circuit connections and vias150 and electrostatic coupling, as well as impurities and particle contamination introduced during fabrication. Each of these factors can substantially affect the overall performance of the chip across its different tiers.

Surface planarization

2D semiconductors are promising for scaled FETs with sub-1-nm channel thickness. However, the reliability of these scaled FETs faces challenges due to defects caused by surface roughness and irregularities at the interfaces between 2D materials and dielectrics151. Moreover, transferring 2D materials onto non-planarized surfaces can introduce strain, negatively affecting device performance152. Additionally, the non-uniformity of growth substrates can lead to variability in device performance among different 2D FETs153, a problem that intensifies when synthesizing 2D materials at low temperatures on various substrates34. In 2D FETs utilizing high-κ dielectrics, the importance of smooth surfaces escalates as devices become thinner, to prevent dielectric disorder154. Consequently, planarization — a process designed to create uniform, ultra-smooth and defect-free surfaces — is crucial in the semiconductor industry. It enhances lithography and etch yields, mitigates step coverage issues, prevents electromigration, reduces contact resistances and addresses metallization challenges155.

Currently, chemical mechanical polishing (CMP) is the most widely used planarization technique, achieving ultra-smooth and flat surfaces by combining mechanical forces with chemical reactions156. CMP involves pressing the substrate against a rotating polishing pad and applying a polishing slurry, as illustrated in Fig. 4a. This slurry, consisting of chemicals and abrasives, facilitates chemical reactions and, together with the controlled hardness and force applied to the substrate, effectively removes material157. The composition of the slurry — abrasives, corrosion inhibitors, complexing agents, pH regulators, and dispersants or surfactants — is tailored to the materials being removed158. The interaction of the slurry with different materials at the substrate interface requires careful studies. Determining the optimal material removal rate involves analysing factors such as slurry composition, mechanical force, pad texture and hardness, heat generation and platen rotation velocity159. Various models have been developed to analyse wafer–pad contact, lubrication and the chemical reactions between the slurry and metals or dielectrics to prevent defects such as metal dishing, oxide erosion and corrosion160,161,162. Thermal models address issues such as metal film delamination caused by heat during CMP163,164,165. At present, research focuses on reducing defects, developing CMP fill synthesis166,167,168, improving post-CMP cleaning methods and creating environmentally friendly slurries169. With advances in 2D electronics, testing new materials for semiconducting channels, dielectrics, contacts, vias and interconnects becomes crucial. This emphasizes the need for refined CMP methodologies for 3D ICs based on 2D electronics, requiring thorough analysis of chemical and mechanical interactions at the wafer interfaces145.

Fig. 4: Design considerations and challenges for 3D integration with 2D electronics.
figure 4

a, Schematic of a typical chemical mechanical polishing setup consisting of rotating polishing pads, chemical slurry and so on with a wafer carrier. b, Thermal management challenges associated with 2D materials. They include high out-of-plane thermal insulation of 2D materials and integration obstacles for heat spreaders. c, Electrostatic coupling and interconnects. 2D materials like graphene can potentially be incorporated as barriers to prevent electrostatic interference. Since 2D-based 3D integration can potentially decrease the tier thickness considerably, it is important to keep up with the latest innovations in silicon technology such as back-side power delivery networks, air-gap integration, low-κ interlayer dielectrics (ILDs) and the introduction of new interconnect materials, which may be adopted for 2D electronics. BEOL, back-end-of-line.

Thermal management

Planar 2D ICs utilize bulk Si, thermal interface materials and heat sink structures for efficient thermal management170,171. However, for 3D ICs, the increased device and power density leads to higher heat generation. This issue is compounded by the difficulty of accessing and creating adequate thermal dissipation paths in the upper tiers, exacerbating the impact of heat. Exposure to higher temperatures can cause signal delays and accelerate ageing, thereby reducing the chip’s lifetime. Therefore, it is crucial that every design step for a 3D IC incorporates thermal considerations. Effective heat dissipation from thermal hotspots in a 3D IC requires materials with high thermal conductivity and thermal vias or pathways that have a low overall thermal resistance, including at material interfaces. The challenges of thermal management with 2D materials are illustrated in Fig. 4b.

Understanding nanoscale thermal transport in 2D FETs often requires advanced theoretical models alongside experimental research172,173. Studies have explored localized heat generation in 2D electronics174, high thermal isolation between van der Waals layers175, and the effect of thermal expansion coefficient mismatch between 2D materials and substrates176,177. However, in some cases, the use of 2D materials demands new characterization techniques178. For example, in a recent study, a purely experimental approach to extract the in-plane thermal expansion coefficient of 2D TMD monolayers was presented, thereby addressing the large discrepancies in 2D TMD thermal expansion coefficient values in the literature179. In their approach, they utilized Raman spectroscopy to capture the difference in thermal expansion of the 2D material on different substrates caused by the thermal mismatch between the 2D film and the substrate to extract the thermal expansion coefficient. There are also other approaches, using van der Waals materials for both thermal isolation as well as heat-spreading applications. For example, an interesting study reported extremely anisotropic thermal conductors with a room-temperature thermal anisotropy ratio — the ratio of thermal conductivity along the fast axis to that of the slow axis — of 900 for MoS(ref. 180), suggesting that interlayer rotation may be an effective technique to engineer anisotropic thermal properties in 2D materials. Furthermore, graphene and related materials have been shown to be effective heat spreaders, potentially replacing traditional heavier materials such as aluminium and copper181,182. These experimental studies are propelling the field towards a more thermal-focused research on 2D VLSI chips. This includes the development of thermally conductive vias, spreaders, heat sinks, microfluidic channels, and other design and packaging solutions for 3D integration of 2D electronics. Various results and techniques mentioned above must be coupled with models and studies of densely integrated chips.

Parasitic capacitance

The impact of parasitic capacitance and electrostatic coupling between conductive elements must be carefully considered in the physical design of 3D ICs, because these can lead to detrimental effects such as signal degradation or delay, noise and crosstalk183,184. At the device level, these electricalf interferences can cause unwanted changes in threshold voltage and increased power consumption149,185. Therefore, during the layout stage, the routing, placement and spacing between various components should be meticulously analysed to account for capacitive coupling. This analysis necessitates the use of appropriate low-κ dielectric materials, shielding layers and grounding planes186,187. However, considerations must also extend to interface properties, thermal conductivity and the coefficient of thermal expansion when selecting materials. Additionally, 2D materials, such as graphene, have been proposed as electrostatic screening layers (Fig. 4c). To enhance the screening efficiency of graphene, even at high-frequency regimes (up to 500 GHz), doping has been proposed, based on evaluations of its electrostatic screening properties50. Continuous innovations in silicon technology — including interconnects, power delivery and interlayer dielectrics — remain essential because they are likely to be integrated with 2D electronics in the future.

Architectural design considerations

After determining the desired devices, functionalities, corresponding materials and associated fabrication processes, identifying the optimal integration approach becomes the subsequent crucial step. This requires a comprehensive electrical-design-automation tool flow to ensure seamless incorporation while upholding the performance standards of the 3D IC188. A primary step towards 3D integration is tier partitioning, which involves dividing the 3D IC into distinct tiers based on functionality, fabrication processes, power delivery and thermal management. This division can occur at the transistor level, the block level or the gate level.

At the transistor level, the n-type and p-type transistors of each standard cell are placed in different tiers without the need for advanced tier-partitioning algorithms. At the block level, tier partitioning divides tiers according to functional blocks, such as logic, memory, power and input–output functionality. Even though block-level tier partitioning simplifies integration complexities, gate-level partitioning offers the most design flexibility. Here, optimization of signal propagation, minimization of interconnect lengths, and improvements in performance and efficiency are achieved by grouping gates and associated interconnects according to the critical paths that minimize connections between critical components for ease of signal propagation, functionality, connectivity, thermal management, clock domains, and so on. There are several methods and algorithms to perform tier-partitioning at the block and gate levels for silicon-based 3D ICs189,190,191,192,193,194. Incorporating thermal analysis and optimization techniques into these tier-partitioning methods is crucial, especially when using 2D materials and thin (less than 1 µm) tiers.

Another critical design step for 3D ICs is 3D placement, where the optimal physical locations of different functional blocks are determined on the basis of signal delays, power distribution, thermal management, and so on. 3D placement approaches (or 3D placers) aim to address performance, voltage-drop and thermal hotspot issues by optimizing routing congestion and critical path timing. They place power-hungry components close to power sources and thermally sensitive components close to heat sinks. There are two types of 3D placer: pseudo-3D placers195,196, which treat the 3D IC as a planar design using 2D placement algorithms, and true-3D placers197,198,199, which consider the 3D vertical stacking nature of IC and inter-tier via connectivity.

Following tier partitioning and 3D placements, the next step is the design of a 3D clock delivery network. This network is crucial for distributing clock signals within a 3D IC, ensuring signal integrity and synchronization of different components to operate at the desired clock frequency. Key considerations include clock distribution, clock tree synthesis, power and ground distribution, crosstalk and noise mitigation, and thermal optimization200.

There are several approaches and examples of tier partitioning, 3D placers and 3D clock delivery networks, developed for silicon-based 3D ICs and designs based on through-silicon vias, and complemented with thermal analysis and optimization techniques. As 2D electronics matures, modifying current solutions or developing techniques for the physical design of 2D FET-based monolithic 3D ICs will become critical.

3D testing

3D IC testing is the final step in assessing the industrialization potential of 2D-based 3D chips. It is crucial to recognize that various defects and potential faults must be anticipated as testing solutions are developed. Some sources of defects include those arising from fabrication process variations, voids or defects in the interlayer dielectric, and resistive opens or shorts in interconnects or vias201,202. Additionally, it is important to consider the effects of heating and ageing on performance degradation in 3D ICs171. The effects of various defects will also depend on the design considerations made during the tier partitioning, placing and 3D clock delivery network design steps. Therefore, it is essential to integrate test solutions concurrently with the development of the physical design188. Ultimately, expanding current delay fault models203,204 and associated design-for-test solutions188,205,206 to accommodate 2D VLSI chips will become critical.


We have delved into diverse topics, including the advance towards very-large-scale integration in 2D electronics, as well as the progress, opportunities and design considerations related to 3D integration of 2D electronics. 3D integration with 2D semiconductors offers remarkable benefits, such as the potential for scaling transistors and increasing device density, and also the development of multifunctional chips through the incorporation of non-computational devices in a 3D architecture. We hope that this Review not only elucidates key considerations in the design of 3D integrated circuits based on 2D materials but also stimulates increased interest in this exciting field.