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A Long Short-Term Memory for AI Applications in Spike-based Neuromorphic Hardware

A preprint version of the article is available at arXiv.


Spike-based neuromorphic hardware holds promise for more energy-efficient implementations of deep neural networks (DNNs) than standard hardware such as GPUs. But this requires us to understand how DNNs can be emulated in an event-based sparse firing regime, as otherwise the energy advantage is lost. In particular, DNNs that solve sequence processing tasks typically employ long short-term memory units that are hard to emulate with few spikes. We show that a facet of many biological neurons, slow after-hyperpolarizing currents after each spike, provides an efficient solution. After-hyperpolarizing currents can easily be implemented in neuromorphic hardware that supports multi-compartment neuron models, such as Intel’s Loihi chip. Filter approximation theory explains why after-hyperpolarizing neurons can emulate the function of long short-term memory units. This yields a highly energy-efficient approach to time-series classification. Furthermore, it provides the basis for an energy-efficient implementation of an important class of large DNNs that extract relations between words and sentences in order to answer questions about the text.

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Fig. 1: Schematics and dynamics of a two-compartment LIF neuron model with AHP currents.
Fig. 2: PSPR, gradient transmission and energy consumption of AHP-SNNs for the sMNIST task.
Fig. 3: Spiking RelNet implementation with very sparse firing.
Fig. 4: Voltage regularization and its capability to enforce a sparse firing regime in combination with spike rate regularization.
Fig. 5: Spiking RelNet placement and optimization on Loihi.

Data availability

The MNIST dataset13 is freely available at The bAbI dataset16 is freely available at

Code availability

The Loihi source code is freely available from Github at


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This research/project was supported by the Human Brain Project (grant agreement number 785907 and 945539, both to W.M.) of the European Union and a grant from Intel (to W.M.). Special thanks go to G. Bellec and D. Salaj for their insightful comments and ideas when carrying out this work.

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Authors and Affiliations



A.R., P.P. and W.M. contributed to the design and planning of the experiments. A.R. and P.P. carried out the experiments. A.R., P.P., A.W. and W.M. participated in the analysis of the experimental data. A.R., P.P., A.W. and W.M. wrote the manuscript.

Corresponding author

Correspondence to Wolfgang Maass.

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Competing interests

P.P. and A.W. are currently employed by Intel Labs, developers of the Loihi neuromorphic system. W.M. and A.R. are members of the Intel Neuromorphic Research Community and W.M. has received research funding from Intel for related work.

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Nature Machine Intelligence thanks Jianhua Yang, Tara Hamilton and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary Figs. 1 and 2, Tables 1–5 and details of the benchmarking, tasks and parameters.

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Rao, A., Plank, P., Wild, A. et al. A Long Short-Term Memory for AI Applications in Spike-based Neuromorphic Hardware. Nat Mach Intell 4, 467–479 (2022).

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