Atomic-scale Control of Tunneling in Donor-based Devices

Atomically precise donor-based quantum devices are a promising candidate for solid-state quantum computing and analog quantum simulations. However, critical challenges in atomically precise fabrication have meant systematic, atomic scale control of the tunneling rates and tunnel coupling has not been demonstrated. Here using a room-temperature grown locking layer and precise control over the entire fabrication process, we reduce unintentional dopant movement while achieving high quality epitaxy in scanning tunnelling microscope (STM)-patterned devices. Using the Si(100)2×1 surface reconstruction as an atomically-precise ruler to characterize the tunnel gap in precision-patterned single electron transistors, we demonstrate the exponential scaling of the tunneling resistance on the tunnel gap as it is varied from 7 dimer rows to 16 dimer rows. We demonstrate the capability to reproducibly pattern devices with atomic precision and a donor-based fabrication process where atomic scale changes in the patterned tunnel gap result in the expected changes in the tunneling rates.


Introduction
Atomically precise silicon-phosphorus (Si:P) quantum systems are actively being pursued to realize universal quantum computation 1 and analog quantum simulation. 2 Atomically precise control of tunneling rates is critical to tunnel-coupled quantum dots and spin-selective tunneling for initialization and read-out in quantum computation, [3][4][5] and also essential in tuning correlated states in Fermi-Hubbard simulators. 2 Although scanning tunneling microscope (STM)-patterned tunnel junctions lack the degree of tunability of top-gate defined tunnel barriers in conventional semiconductor heterostructures, 6 it was shown by Pok 7 and Pascher et al. 8 that engineering the dimensions of the STM-patterned nanogaps can affect the tunnel barriers and the tunnel rates in STM-patterned devices: even a ~1 nm difference in the tunnel gap separation can drastically change the tunnel barrier and transport properties in atomically precise Si:P devices. 9 Although the exponential dependence of the resistance on the tunnel gap at the atomic scale is a well established physical phenomenon, critical challenges in fabrication have meant a systematic demonstration of the exponential dependence of the resistance on the tunnel gap separation has not been demonstrated in STM patterned devices. Here using a room-temperature grown locking layer and precise control over the fabrication process, we demonstrate the expected control of the tunnel coupling in response to atomic-scale changes in STM-patterned single electron transistors (SETs). In this study, we define "atomic-scale control of tunneling" as achieving the predicted response in the tunneling resistance relative to a given atomic scale change in the tunneling gap.
(For example, if the dimension of a tunnel gap is 11 dimer rows, and the gap is changed by 1 dimer row, there is an expected one order of magnitude change in tunneling resistance.) We mention here that reliable device metrology is possible at two stages, measuring the STM lithographic pattern dimensions on an atomically ordered surface, and low temperature transport measurements of the resulting device. Using the naturally occurring surface lattice of the Si(100)2×1 surface reconstruction as an atomically-precise ruler, we measure the tunnel junction gap separations based on the number of lattice counts in the surface reconstruction and demonstrate exponential scaling of the tunneling resistance where the gap is varied from 7 dimer rows to 16 dimer rows. Varying the tunnel gap separation by only ~5 dimer rows, we demonstrate a transition in SET operation from a linear conductance regime to a strong tunnel coupling regime to a weak tunnel coupling regime. We characterize the tunnel resistance asymmetry in a pair of nominally identical tunnel gaps and show a fourfold difference in the measured resistances that corresponds to half a dimer row difference in the effective tunnel gapthe intrinsic limit of hydrogen lithography precision on Si(100)2×1 surfaces.
In this study, we overcome previous challenges by uniquely combining hydrogen lithography that generates atomically abrupt device patterns 10,11 with recent progress in low-temperature epitaxial overgrowth using a locking-layer technique [12][13][14] and silicide electrical contact formation 15 to substantially reduce unintentional dopant movement. These advances have allowed us to demonstrate the exponential scaling of the tunneling resistance on the tunnel gap separation in a systematic and reproducible manner. We suppress unintentional dopant movement at the atomic scale using an optimized, room-temperature grown locking layer, which not only locks the dopant position within lithographically defined regions during encapsulation, but also improves reproducibility since the critical first few layers are always grown at room temperature. 12 Furthermore, our recent development of a high-yield, low-temperature method for forming ohmic contact to burried atomic devices enables robust electrical characteriation of STMpatterned devices with minimum thermal impact on dopant confinement. 15 With improved capabilities to define and maintain atomically abrupt dopant confinement in silicon, we fabricated a series of STM-patterned Si:P single electron transistors (SETs), where we systematically vary the tunnel junction gap separation, and have used them to demonstrate and explore atomic-scale control of the tunnel coupling. Instead of geometrically simpler single tunnel junctions, we chose SETs in this study because observation of the Coulomb blockade signature is a direct indication that conductance is through the STM-patterned tunnel junctions.
We chose SET leadwidths and island size to be large enough that we are in the metallic regime and avoid the complications introduced by quantization and confinenment in smaller lead widths.
Additionally, SETs are well-understood devices that are ideal for developing and validating atomic-scale control of device designs and fabrication methods. They enable characterization of capacitive coupling between the various gates and device elements, the two junctions that make up an SET are fabricated in a nearly identical process and can be individually characterized, electron addition/charging energies can be measured and compared to design values, and current flowing through the SET island shows a strong exponential dependence on the junction dimensions at the atomic scale. Furthermore, SETs are exemplary structures because they are fundamental components in a number of quantum devices: they can function as DC charge sensors and are used in spin to charge conversion, qubit initialization, charge noise characterization, radio-frequency (RF)-SET reflectometry, and charge pumps.

Atomically precise patterning of tunnel gaps
We define the tunnel gaps with atomically abrupt edges using ultra-clean hydrogen lithography while utilizing the surface lattice of the Si(100)2×1 surface reconstruction to quantify the tunnel gap separations with atomic-scale accuracy. The Si(100)2×1 surface reconstruction features dimer rows of pitch 0.77 nm that can serve as a natural "atomic ruler" allowing us to define the critical dimensions with atomic precision. Figure 1 shows atomically precise STM lithography for three SET charge sensors fabricated with nominally identical source/island and drain/island tunneling gaps. In these devices we targeted an 11 dimer row tunnel gap for the source/island/drain tunnel coupling for all three devices. In this set of devices our fabrication control resulted in a mean gap of 11.0 dimer rows with a standard deviation of the mean of 0.2 dimer rows (1 sigma). (See Table 1) Figure 1. Scanning tunneling microscopy (STM) images of the central parts of a series of chargesensing donor/quantum dot devices. The bright areas are STM-patterns where the hydrogen-resist has been removed, exposing the chemically reactive dangling bonds. (a) (b) (c) High-resolution STM images of the lithography patterns of donor clusters and single electron transistor (SET) charge sensors. We name the devices in panels (a), (b), and (c) as Device A, Device B, and Device C in Table 1.  Figure 1. the SET island is treated as a capacitor. Gate voltage is applied to both gates in parallel with respect to the grounded source. The drain-source bias is applied to the drain contact lead with respect to the grounded source. (e) The energy diagram of an SET, where and are the chemical potentials of the source and drain leads respectively;

Controlled variation of the tunnel gap in donor-based SETs
( ) is the chemical potential of the island that is occupied with excess electrons.
is the mean barrier height above the Fermi level.  Figure 2 (b) shows an STM image of the atomically precise central region of a typical SET device after hydrogen-lithography, but before phosphine dosing. P dopants only incorporate into the bright regions where the STM tip has removed H atoms from the hydrogenterminated surface and exposed chemically reactive Si-dangling bonds. (Figure 2 (c)) The planar source and drain, island (quantum dot), and gates are saturation-dosed resulting in degenerate dopant densities over three orders of magnitude beyond the Mott metal-insulator transition. 16 The island is capacitively coupled to the two in-plane gates through an effective capacitance and to the source (drain) electrodes through tunnel barriers represented by a tunneling resistance ( ) and a capacitance ( ), where each resistance is coupled in parallel with its respective capacitance ( Figure 2 (d)). The gate voltages applied to both gates tune the local electrochemical potential of the island and modulate the source-drain current flowing through the central island.
Single electrons tunnel sequentially through each barriers due to the electron addition energy (charging effect) on the island. 17 (Figure 2 Table 2. Critical dimensions of the hydrogen lithography patterns from the high-resolution scanning tunneling microscopy (STM) images (shown in Figure 3), where STM imagebroadening artifacts have been corrected. The total pattern areas (in units of squares, or the length-width aspect ratio of the STM-patterned leads) from the source and drain leads between the two inner contact probes (see Figure 2 (a)) are also given. The uncertainties in the number of squares is dominated by the uncertainty in the e-beam alignment between the electrical contacts and the STM-patterned contact pads. The right-most column of the table lists the measured total junction resistances ( + ), where corrections have been taken to eliminate contributions from the source and drain lead sheet resistance. The + for the single electron transistor (SET) device named SET-B represents an ohmic resistance where the uncertainty is dominated by uncertainty in estimating the number of squares in the source/drain leads. The + for SET-C to SET-I represents tunneling resistances where the error bars include contributions from both the variation (one standard deviation) in the Coulomb oscillation peak height over the corresponding gating range (-200 mV to 200 mV, see Figure 4 (b)) from multiple gate sweeps and the uncertainty in the subtracted source and drain leads resistance. The uncertainty in the reported dimensions and tunneling resistance values are given as one standard deviation in the distribution of measurement samples.  Table 2 for all devices in this study (See Methods for details). In addition, our regular use of high-resolution STM imaging over the STM-patterned device region allows us to identify atomic-scale defects in the device region, such as step-edges 18 and buried charge defects, 19 which can potentially affect device performance. (approximately 57 ± 4 squares between the e-beam patterned voltage contact probes, see Figure   2(a)), this corresponds to a sheet resistance of 1.70 ± 0.15 kΩ in the STM-patterned electrodes, in excellent agreement with previous results on metallically doped Si:P delta layers. 20 Given the ultrahigh carrier density and small Thomas Fermi screening length 16 in this saturation-doped Si:P system and the relatively large island size 21 of the SETs, we treat the energy spectra in the islands and source and drain leads as continuous (∆ ≪ , where ∆ is the energy level separation in the island and source and drain reservoirs) and adopt a metallic description of SET transport. 17 The tunneling rates, , , and the tunneling resistances, , = ℏ/(2 2 | | 2 ), across the source and drain tunnel barriers can be described using Fermi's golden rule, 22 where is the tunneling matrix element, , represents the initial and final density of states, ℏ is the reduced Plank's constant, and is the charge of an electron.

Exponential scaling of tunneling for atomic scale changes
In the interest of clarity, we define our use of the terms tunnel coupling and tunneling rates. In the context of the work presented here, Equation 1 relates the tunneling rates to the tunneling resistance values where the tunneling matrix elements, , represent the tunnel couplings for our system. However, it should be noted that the term "tunnel coupling" is also widely used in the context of quantum dots, where the tunnel coupling is a measure of level broadening of the energy eigenstates on the quantum dots and can lead to a loss of electron localization on the dot in the strong tunnel coupling regime. The term is also used in analog quantum simulation where the tunneling coefficient in the Hubbard Hamiltonian denotes the hopping energy or tunnel coupling strength between adjacent sites.
In the following, we show that the total tunneling resistance + of an SET can be extracted by measuring, at zero drain-source direct current (DC)-bias, the peak amplitudes of the differential conductance Coulomb oscillations, as shown in Figure 4 Table 1), and assuming energy independent tunnel rates and density of states in a linear response regime, Beenakker and co-workers 23,24 have shown that the peak amplitude of the zero-bias differential conductance oscillations in an SET reduces to the following temperature independent expression for arbitrary and values, where and are conductances through the source and the drain tunnel barriers, is the density of state in the metallic island, and the density of states in the leads is embedded in the tunneling rates.
In Figure 4 Figure 4(d)) blurs the charge quantization on the island and introduces finite conductance within the Coulomb diamonds through higher order tunneling processes (co-tunneling). 28 In the weak tunnel coupling regime in SET-F (see Figure   4(e)), the Coulomb blockade diamonds become very well established. Tuning the tunnel coupling between strong and weak coupling regimes in atomic devices is an essential capability: e.g. for simulating non-local coupling effects in frustrated systems. 29 It has been found essential for capacitance modeling (See Supplementary Table 1 ) Table 2) and adopt an averaged value of = 12 nm in the WKB simulation. We account for the "electrical geometry" of the devices by assuming an electrical thickness of = 2 nm, 26 while treating the lateral electrical seam width, , and the mean barrier height, , as fitting parameters. We obtain 100 ± 50 meV as the best-fit barrier height (uncertainty represents two ), which is in good agreement with the theoretically predicted range of Fermi levels below the Si conduction band edge in highly -doped Si:P systems, ~80 meV to ~130 meV, from tight-binding 26 and density functional theory 25 calculations. A similar barrier height value (~80 meV) has also been experimentally determined in a Fowler-Nordheim tunneling regime by Fuhrer's group using a similar STM-patterned Si:P device. 8 We obtain 3.1 ± 0.4 nm as the best-fit seam width (uncertainty represents two ), which is in good agreement with the Bohr radius of isolated single phosphorus donors in bulk silicon (~2.5 nm). 25 Using the best-fit seam width from the WKB simulation, we also find good  Figure 3 were fabricated in series from two different ultra-high vacuum scanning tunneling microscope (UHV-STM) systems with similar but non-identical hardware platforms using the same nominal methods and processes.  influences the tunnel current in the Coulomb blockade transport regime, as has been previously suggested by Pascher et al. 8 Other factors that can affect the tunnel barrier and therefore cause tunnel resistance variability include changes to the local potential landscape due to buried charge defects near the device region in either the substrate or the overgrowth layer. From the exponential dependence in Figure 4 (c), a factor of four corresponds to an uncertainty in the gap separation of only about half of a dimer row pitch distance, which represents the ultimate spatial resolution (a single atomic site on the Si(100)2×1 reconstruction surface) and the intrinsic precision limit for the atomically precise hydrogen-lithography.

Discussion
The results presented here are of interest where critical device dimensions and pattern fidelity or tunnel coupling play a direct role in device performance. Complex devices such as arrays of quantum dots for analog quantum simulation, have stringent requirements with respect to site-to-site tunnel coupling. While the details of the tunneling characteristics are different than an SET in the metallic regime, the fabrication methods described here are applicable to fabrication of single or few atom quantum dots and should aid in achieving a higher degree of reproducibility in those devices. 32 In summary, we have demonstrated the ability to reproducibly pattern devices with atomic precision, and that improved locking layer methods coupled with meticulous control over the entire donor-based device fabrication process resulted in STM patterned devices with predictable tunneling properties. By using the natural surface reconstruction lattice as an atomic ruler, we systematically varied the tunneling gap separations from 7 dimer rows to 16 dimer rows and demonstrated exponential scaling of tunneling resistance consistent with atomic scale changes in the tunneling gap. We emphasize that, critical fabrication steps, such as a defect-and contaminant-free silicon substrate and hydrogen resist formation, atomically abrupt and ultraclean hydrogen lithography, with dopant incorporation, epitaxial overgrowth, and electrical contact formation that suppress dopant movement at the atomic scale, are all necessary to realize devices with atomic precision. This study represents an important step towards fabricating key components needed for high-fidelity silicon quantum circuitry that demands unprecedented precision and reproducibility.

STM-patterned donor-based device fabrication
The Si:P single electron transistors (SETs) are fabricated on a hydrogen-terminated Si(100)2×1 substrate (3 × 10 15 cm −3 boron doped) in an ultrahigh vacuum (UHV) environment with a base pressure below 4 × 10 −9 (3 × 10 −11 Torr). Detailed sample preparation, UHV sample cleaning, hydrogen-resist formation, and STM tip fabrication and cleaning procedures have been published elsewhere. 11,18,33 A low 1×10 -11 Torr UHV environment and contamination-free hydrogen-terminated Si surfaces and STM tips are critical to achieving high-stability imaging and hydrogen lithography operation. The device geometry is defined by selectively removing hydrogen resist atoms using an STM tip in the low-bias (3~5 V) and high-current (15~50 nA) regime where the small tip-sample separation allows for a spatially focused tunneling electron beam under the atomic-scale tip apex, creating hydrogen lithographic patterns with atomically abrupt edges. For complete hydrogen desorption within the patterned regions, the typical tip scan velocity and scan-line spacing are 100 nm sec -1 and 0.5 nm line -1 respectively. We then saturation-dose the patterned device regions with PH3 followed by a rapid thermal anneal at 350 ℃ for 1 min to incorporate the P dopant atoms into the Si surface lattice sites while preserving the hydrogen resist to confine dopants within the patterned regions. The device is then epitaxially encapsulated with intrinsic Si by using an optimized locking layer process to suppress dopant movement at the atomic-scale during epitaxial overgrowth. 12,14 The sample is then removed from the UHV system and Ohmic-contacted with e-beam defined palladium silicide contacts. 15

Low-temperature transport measurements
Low-temperature transport measurements are performed using either a closed-cycle cryostat at a base temperature of 4 K or a dilution refrigerator at a base temperature of ~10 mK. For SET-B to SET-G, the zero-DC bias differential conductance ( 0 ) are measured using 0.1 mV AC excitation at 11 Hz. For SET-H and SET-I, 0 is numerically estimated from the measured DC Coulomb diamonds. We calibrate the zero drain-source bias level by mapping out complete Coulomb diamonds, where the intersections of the Coulomb diamonds represent the true zerobias condition across the source-drain leads. We extract the zero-bias conductance curves (as shown in Figure 4) from the measured Coulomb diamond diagrams. Since the effect of gate voltage compensation on the SET island's chemical potential is insignificant under our measurement conditions at 4 K, we did not compensate when measuring or calculating / at the zero drain-source bias for extracting the tunnel resistance values. The gate leakage currents are on the order of ~10 pA or less within the gating range used in this study.

Characterization of STM lithographic pattern dimensions
We estimate the critical dimensions of the STM-patterned tunnel junctions in a SET from the STM topography images in Figure 3 of the main text, where the gap-distance, , is the average across the full junction width, , using both junctions. The junction width is the average over the island and the first 15 nm of the source and drain leads near the island. The hydrogen lithography and STM-imaging are carried out using different tips and/or under different tip conditions. To eliminate the STM image-broadening due to the convolution between the wavefunctions of the tip apex and Si danging bonds and extract the boundary of the hydrogen-depassivated surface lattice sites, we estimate the image-brodening, ∆ , from the difference between the imaged single dangling bond size, , (full-width at half maximum (FWHM)) and the size of a single dangling bond lattice site, 0 , where we have assumed 0 equals half a dimer row pitch. (see Figure 2 (c)). The image-broadening, ∆ = − 0 , is then used to correct the critical dimensions that are read out from the half-maximum height positions in the STM topography images.

Theoretical modeling of SETs
The theoretical analysis of the transport through SETs is based on an equivalent circuit model (see Figure 2 (d)) under a constant interaction approximation. The analytical expressions regarding the equilibrium drain-source conductance in the main text are derived using the standard Orthodox theory under a two-state approximation. 21,34

Data Availability
All relevant data are available upon request from the authors.
We fit the measured tunneling resistance + as a function of the scanning tunneling microscope (STM)-patterned tunnel gap separation, , using the well-known Wentzel-Kramers-Brillouin (WKB) formulation in the low-bias (linear response) regime. 1,2 We adopt a generalized formula for the tunnel effect through a potential barrier of arbitrary shape between two similar metallic electrodes, ignoring the image force correction to the barrier potential when an electron approaches the dielectric barrier interface. We define which represents the zero-bias mean barrier height above the Fermi level, where ( ) is the true barrier above the Fermi level, ∆ = 2 − 1 is the barrier separation, and 2 and 1 are the limits of the barrier at the Fermi level. We expect the exponential dependence of the tunnel conductance on both the mean barrier height and barrier width, whereas the model predicts a linear dependence on the tunneling cross-section area. Therefore, the slight width variation among the fabricated tunneling junctions is assumed to have minor effects on the tunnel conductance. We assume a uniform electrical thickness = 2 nm for the STM-patterned device components. To account for the finite electron density extension beyond the hydrogen-lithography patterns in the lateral directions, we add a uniform lateral seam, , to the device pattern. We adopt an averaged width of = 12 nm as the STM-patterned junction width. Therefore, the electrical junction width is expressed as ( + 2 ) and ( + 2 ) represents the electrical tunnel junction cross-sectional area. We express the barrier width ∆ = ( − 2 ) with respect to the measured tunnel gap separations based on STM images and the parameterized electrical seam width that comes from capacitance measurements and simulation. The lateral seam width, , and the mean barrier height, , are treated as fitting parameters. The WKB tunneling resistance, , in the low-bias regime is expressed in Supplementary Equation 1 Where ℎ is Plank's constant, is the charge of a single electron, and * is the effective mass of the conducting electrons. Conductivity in the degenerately -doped silicon-phosphorus (Si:P) electrodes is assumed to be dominated by the lowest energy sub-bands, with effective mass * = 0.21 as measured by Miwa et al. using direct spectroscopic measurement in blanketdoped Si:P layers, 3 where is the free electron mass. We point out that, at a given mean barrier height , the dependence of WKB tunneling resistance, , on the gap separation, , deviates from an ideal exponential behavior, especially at small gap separations, due to the prefactor in front of the exponential term in Supplementary Equation 1.

Supplementary Note 3: Comparison between the Measured and Simulated Capacitances in STM-patterned SET Devices
Capacitance modeling of STM-patterned Si:P devices has demonstrated success in accurately predicting the device electrostatics down to the atomic scale. 4 Supplementary Table 1 compares the experimentally observed SET capacitances and the simulated capacitances, where the device components are treated as metallic sheets in the shape of the "electrical geometry" of the device. 4,5 A uniform electrical thickness of z=2 nm in the z-direction is assumed for both the Simulation 1 and Simulation 2. No lateral electrical seam is added to the hydrogen lithography pattern in Simulation 1. The simulated capacitances from Simulation 1 agree poorly with the measured capacitances. In Simulation 2, a lateral electrical seam width of 3.1 nm from the WKB tunneling resistance fit is added to the STM-patterned device geometry, which significantly improves the agreement between the simulated and measured capacitances. The experimental and simulated charging energy, C , and capacitances of the single electron transistor (SET) device named SET-G in the main text. Σ represents the total capacitance of the SET island. G , S , and D represent the capacitance between the SET island and the gates, the source lead, and the drain lead, respectively. The experimental capacitances are extracted using the height and width of the measured Coulomb diamonds (Figure 4 (a) in the main text) as well as the slopes of the positive and negative diamond edges. 6 The uncertainties result from the experimental determination of the Coulomb diamond dimensions from the measured Coulomb diamonds while extracting the experimental capacitances. The capacitance simulation is carried out using a finite-element 3D Poisson solver, FastCap. 7,8

Supplementary Note 4: Quantifying Individual Junction Resistances in a Metallic SET
Following the well-established Orthodox theory for a metallic SET, 9 the tunneling resistance across the individual tunnel barriers can be extracted from the peak shapes of Coulomb oscillations in . In this section, we derive the explicit expressions in Equation 2 of the main text using an analytical model that was first proposed by Inokawa and Takahashi. 10 The tunneling probability through an SET is determined by the change in the SET's Helmholtz's free energy = − , where is the total electrostatic energy stored in the system and is the work done by voltage sources, due to a single electron tunneling event. Following the constant interaction model in a metallic regime (See Figure 2 (d) in the main text), the change in when an electron tunnels from the source/drain electrodes to the island and transitions the number of excess electrons on the island from to + 1 can be expressed as ∆ , +1, = − , + ( ), where , and ( ) are the chemical potential of the source/drain leads and an SET island with excess electrons. 11 In the zero-temperature limit, = 0 K, the tunneling rates can be expressed using Fermi's golden rule. Where Θ( ) is a unit step function. For simplicity, we have assumed the single electron tunneling events to be elastic without electromagnetic interactions between the tunneling electron and the environmental impedance. 12 In an equilibrium condition, the stationary occupancy probability, ( ), of the SET island (with excess electrons) can be derived by requiring ( )/ = 0 in a steady state master equation 6 and obtaining ( )( +1, + +1, ) = ( + 1)( , +1 + , +1 ). At low-temperatures where ≪ , only the two most-probable charge states dominate the SET island occupancy at a given bias. Adopting a two-state approximation, 10 ( ) + ( + 1) = 1, an analytical expression of the total drain-source current through the SET can be obtained, Using the expression of ( ) from the constant interaction model, 11  where 0 (| 0 | ≤ 2 ) represents a fractional electron charge that is present on the island when the voltage electrodes are floating, typically due to background charges from the environment. Taking > 0 at = 0 K for instance, the source and drain junction tunneling resistances can be derived from the right derivative at the leading edge, where = = ( + To estimate the drain and source tunneling resistances from the Coulomb oscillation peaks that are measured at finite temperatures, we approximate the asymptotic slopes at the leading and trailing edges by fitting the leading and trailing slopes of the measured Coulomb oscillation peaks.