## Introduction

Atomically thin two-dimensional (2D) van der Waals layered materials are chemically inert with no dangling bonds. This allows for exploring a unique facet of science as well as expanding the realm of practical applications to soft and wearable electronics, with high transparency1 and stretchability2,3. The recently developed wafer-scale 2D materials, such as graphene (Gr)4,5,6, transition-metal dichalcogenides (TMdCs)7,8, and their heterostructures9, combined with the state-of-the-art top-down technology, further allow for integration of the complementary metal–oxide–semiconductor components.

Graphene exhibits high carrier mobility at room temperature, but poor switching capability4,5,6,10,11,12. Meanwhile, the semiconducting TMdC counterparts show a high on/off ratio with poor mobility7,8,13,14,15,16,17. Despite tremendous efforts, only marginal improvements have been achieved in the switching capability of Gr18,19 and carrier mobility of TMdCs20,21,22, which are hardly satisfactory for industrial applications. More recently, Gr/MoS2 heterostructures have been implemented to reduce the contact resistance and enhance the device performance for MoS2 via modulation of work function for Gr by an electrostatic gating20. In addition, Gr/MoS2 vertical stacks have been applied to optoelectronics with efficient photocurrent extraction23. In this study, by constructing Gr/MoS2 heterostructures, we propose a platform of Coulomb drag transistor to realize a high on-/off-current ratio of 108 and high carrier mobility of 3700 cm2 V−1 s−1 at room temperature, which has been rarely achieved previously in 2D material-based device platforms4,5,6,7,8,10,11,12,13,14,15,16,17.

## Results and discussion

### Energy barrier between graphene and MoS2

Monolayer Gr and MoS2 were grown separately by chemical vapor deposition (CVD). Later, monolayer MoS2 was transferred onto a SiO2 (300-nm)/p+-Si substrate, followed by Gr transfer to yield the heterostructure (see Supplementary Fig. 1). This stacking process leads to slight p-doping effect on MoS2 in Gr/MoS2 heterostructure due to charge transfer from MoS2 to Gr, resulting in the formation of a vertical energy barrier (EB) at the heterointerface (see Supplementary Note 1). EB is effectively controlled by dual-gate modulation. Figure 1a illustrates a schematic for dual-gated Gr/MoS2 heterostructure to control the carrier type and density in each layer as a function of top $$\left( {V_{{\mathrm{TG}}}} \right)$$ and bottom gates (VBG). Electrical contacts for the Gr and MoS2 layers were separately constructed after stacking both layers (see Supplementary Fig. 1). Ambipolar Gr with a charge- neutrality point (VCNP) and n-MoS2 characteristics is clearly probed via these electrodes (Fig. 1b), similar to the electrical properties of individual layers.

EB is determined by each transfer curve of Gr and MoS2 in the heterostructure under dual-gate modulation24. The electrostatic displacement field has been suggested for EB as evidence for electrical isolation. The net vertical displacement field (ΔD) is defined from displacement fields of top (DTG, 30-nm Al2O3) and bottom gate (DBG, 300-nm SiO2) as given below25:

$${\Delta} {\boldsymbol{D}} = {\boldsymbol{D}}_{{\mathbf{TG}}} - {\boldsymbol{D}}_{{\mathbf{BG}}}$$
(1)
$${\boldsymbol{D}}_{{\mathbf{TG}}} = \frac{{\varepsilon _{{\mathrm{Al}}_2{\mathrm{O}}_3}^\prime \left( {V_{{\mathrm{TG}}} - V_{{\mathrm{CNP}}}} \right)}}{{t_{{\mathrm{Al}}_2{\mathrm{O}}_3}}}$$
(2)
$${\boldsymbol{D}}_{{\mathbf{BG}}} = \, \frac{{\varepsilon _{{\mathrm{SiO}}_2}\left( {V_{{\mathrm{BG}}} - V_{{\mathrm{th}}}(V_{{\mathrm{BG}}})} \right)}}{{t_{{\mathrm{SiO}}_2}}}\\ = \, \frac{{\varepsilon _{{\mathrm{SiO}}_2}\left( {V_{{\mathrm{BG}}} - V_{{\mathrm{th}}}\left( {V_{{\mathrm{TG}}}} \right) \cdot {\Delta} V_{{\mathrm{BG}}}/{\Delta} V_{{\mathrm{TG}}}} \right)}}{{t_{{\mathrm{SiO}}_2}}}$$
(3)

where Vth, $$\varepsilon$$, and t are threshold voltage of MoS2, dielectric constant, and thickness for each dielectric material, respectively. Here, the threshold voltage of MoS2 is extracted from the transfer curves of MoS2 as a function of top gate and calculated from the relation (ΔVBGVTG) between top VTG and bottom gates (VBG, see Supplementary Note 2). Once electrons and holes prevail at MoS2 and Gr, respectively, the net vertical displacement across Gr and MoS2 is positive and the displacement is applied from MoS2 to Gr, resulting in the energy barrier for each carrier in MoS2 and Gr. In the opposite case (negative vertical displacement), the displacement promotes carrier transfer between two layers without the energy barrier. The vertical energy barrier from the displacement field is finally obtained from the following equation: $${\Delta} D \cdot d_{{\mathrm{GM}}} \cdot q$$, where dGM denotes interlayer distance between Gr and MoS2 (~0.4 nm) (Fig. 1c, d). When Gr is p-type near $$V_{{\mathrm{CNP}}}$$ (VTG = −6.2 V) and MoS2 is n-type (VBG = 40 V) at Gr/MoS2, the established vertical displacement energy is over 0.55 eV and becomes larger (~0.72 eV) at higher VTG = −8.2 V, exceeding previously reported eh separation energy of 0.25 eV at Gr/MoS226. This is again confirmed by the Schottky barrier concept; Schottky barrier height ranges from 0 to 0.72 eV at Gr/MoS2 heterostructure27,28 (see Supplementary Note 2). Consequently, the enhanced EB between Gr and MoS2 plays a key role as an electrical insulator in vertical direction, thus mimicking the conventional Coulomb drag configuration29,30,31,32,33,34,35.

### Coulomb drag effect at graphene/MoS2 heterostructure

To verify the Coulomb drag effect and strong interaction at Gr/MoS2 heterointerface, two representative devices were fabricated without an insulating layer. Gr/MoS2 stacks for both devices are fabricated in the same way by transferring monolayer MoS2 onto SiO2/Si substrate, followed by monolayer Gr transfer onto MoS2 (see “Methods”). Channel definition and metallization were performed at larger Gr and smaller MoS2 for the first case (Fig. 2a). To ensure data reliability, various electrical properties were investigated at high current regime (I > 10 nA, see Supplementary Note 3). A drive current flows along Gr (active layer), while the resulting longitudinal potentials in MoS2 (passive layer) and Gr are separately monitored (Fig. 2a). For data analysis, the electrical properties of ambipolar Gr and n-MoS2 are confirmed using the transfer curves in Coulomb drag configuration (Fig. 2b), similar to the electrical properties at the Gr/MoS2 heterostructure (Fig. 1b). The longitudinal potentials of both Gr and MoS2 are almost identical (Fig. 2c), where EB is relatively shallow at the gate biases for n-Gr/n-MoS2 and p-Gr/n-MoS2 near VCNP (Fig. 1 and see Supplementary Note 2). Meanwhile, the potential of MoS2 rapidly drops and approaches to zero in electrically isolated conditions at p-Gr/n-MoS2 heterostructure with a sufficiently high EB, which is clearly distinct from the positive potential at the Gr side. Yet, interlayer carrier transport at Gr/MoS2 edge takes place by interlayer tunneling induced by drain bias through EB, so that the injected carriers move laterally along Gr and MoS2 (schematic in the inset of Fig. 2c). Thanks to the ideally narrow gap at Gr/MoS2, holes in Gr (gray arrow) strongly drag electrons in MoS2 (red arrow) without recombination, resulting in zero or negative potential as a counterflow geometry36. In addition, the thermoelectric effect appears particularly at high drain (drive) current of Gr (active layer), but potential difference between the positive- and negative-current regime is distinct, confirming the presence of Coulomb drag effect in our device (see Supplementary Fig. 6 and Supplementary Note 4).

A similar behavior is observed in the opposite structure with MoS2 (active layer) and Gr (passive layer) with respect to VBG (Fig. 2d–f). The second device was fabricated at larger MoS2 and smaller Gr (Fig. 2d). When a drive current $$\left( {I_{{\mathrm{MoS}}_2}^{{\mathrm{active}}}} \right)$$ is applied through source/drain onto MoS2 (active layer), longitudinal potentials of MoS2 $$\left( {V_{{\mathrm{MoS}}_2}^{{\mathrm{active}}}} \right)$$ and Gr $$\left( {V_{{\mathrm{Gr}}}^{{\mathrm{passive}}}} \right)$$ at the heterostructure are measured (Fig. 2d). Nearly zero and negative potentials are observed for MoS2, while the positive potential is observed for Gr, although the signature is rather weak compared to the previous case (Fig. 2a–c). This clearly indicates that most carriers flow along the MoS2–Gr (at Gr/MoS2)–MoS2 path and holes inside Gr drag electrons inside MoS2 at the heterointerface. It is of note that this anomalous VXX behavior in Gr/MoS2 heterostructure device persists even at T = 2 K with I = 10 μA (see more details later).

### Coulomb drag transistor at graphene/MoS2 heterostructure

We took advantage of a platform of Coulomb drag to demonstrate the high performance of our unique field-effect transistor; this is achieved by connecting MoS2 to the source and drain (and the inner four-probe electrodes) with a dual gate, while Gr is deliberately isolated from other electrodes (Fig. 3a–c). The transfer curve of Gr/MoS2 transistor was measured as a function of VTG at room temperature (Fig. 3d). In Gr/MoS2 transistor, the observed high on-current is attributed to Gr, while the low off-current is ascribed to MoS2, ultimately resulting in a large on-/off-current ratio of ~108. The longitudinal potential of Gr/MoS2 device is positive when VTG > −13 V. More intriguingly, the potential approaches to zero and becomes negative when VTG < −13 V, resembling the Coulomb drag effect (Fig. 2). This is contrasted with the no negative-potential regions in individual Gr and MoS2 devices fabricated by identical procedures on the same wafer (Fig. 3e and see Supplementary Fig. 7).

We further calculated the four-probe field-effect mobility (μFE) using the following relationship:

$$\mu _{{\mathrm{FE}}} = \frac{L}{W}\frac{{g_{\mathrm{m}}}}{{C_{{\mathrm{ox}}}V_{{\mathrm{XX}}}}}$$
(4)

where Cox, gm, L, and W denote net-oxide capacitance per unit area, transconductance, channel length, and width, respectively37. In particular, Gr/MoS2 mobility values were analyzed at VXX 5 mV (below VCNP) to improve data reliability (Fig. 3d). The two-probe-measured μFE is compared with four-probe-measured μFE for Gr and MoS2 at room temperature (see Supplementary Fig. 8). As a whole, the mobility of the Gr/MoS2 device exceeds that of MoS2 and Gr, and more importantly, the divergence in mobility is distinct at VTG < −13 V (Fig. 3f), resulting from the nearly zero potential shown in Fig. 3d. We define two distinct regimes in the Gr/MoS2 device, based on $$V_{{\mathrm{CNP}}}$$ ~ −11 V (white line, Fig. 3f), similar to the individual Gr device. Such a high mobility at p/n regime can be ascribed to the suppressed effective carrier density and carrier–carrier scattering inside MoS2 at a given conductivity. At the n/n regime for heavily n-doped MoS2 and n-type Gr, the electrical properties of the heterostructure are dominated by Gr as the energy barrier at Gr/MoS2 becomes smaller and carrier transfer occurs. Furthermore, MoS2 at Gr/MoS2 reduces the substrate effect from SiO2, so that Gr at the heterostructure gives better mobility, compared to that of individual Gr device. Figure 3g summarizes the excellent performance of our Gr/MoS2 device with remarkably enhanced mobility of 3700 cm2 V−1 s−1 compared to individual Gr or MoS2 devices; in addition, our device retains a high on-/off-current ratio of 108.5,6,11,12,13,15,16 The similar performance was observed with high on-/off-current ratio and mobility in a series of Gr/MoS2 devices, regardless of the sample quality (see Supplementary Note 5).

We further investigate the temperature (T)-dependent transfer curves and threshold voltage from 2 to 300 K. Metal–insulator transition (MIT) also appears in both Gr/MoS2 at VTG ~2 V (Fig. 4a) and MoS2 at VTG ~13 V (Fig. 4b), which is the cross-over point of the conductivity at different temperatures. In general, metallic behavior in MoS2 is observed at high carrier density, which is typical for poor-quality samples with impurities and disorders17. To evaluate the interface quality of our devices, the carrier density (n) is calculated at the MIT point in dual-gate configuration. The carrier densities of the Gr/MoS2 and MoS2 devices at the MIT point are 1.6 × 1013 m−2 and 3.3 × 1013 m−2 at 300 K and 1.1 × 1013 m−2 and 1.2 ×  1013 m−2 at 2 K, respectively, with the corresponding threshold voltages (Fig. 4c). This confirms high quality of the Gr/MoS2 interface, which is necessary for the Coulomb drag effect.

The strong Coulomb drag effect, however, makes the determination of current in MoS2 in Gr/MoS2 device ambiguous, which could consequently lead to over- or underestimation of mobility. In addition, the Gr/MoS2 device consists of two conducting layers (Gr and MoS2) and vertical tunneling barrier. Therefore, the general planar capacitance model may lead to a large discrepancy in the intrinsic mobility of Gr/MoS2. To avoid these ambiguities, the Hall mobility $$\left( {\mu _{{\mathrm{Hall}}}} \right)$$ was determined using the following relationship:

$$\mu _{{\mathrm{Hall}}} = \frac{L}{W}\frac{{V_{{\mathrm{XY}}}}}{{V_{{\mathrm{XX}}}B}}$$
(5)

where VXY and B are the transverse potential and magnetic field, respectively. Both the longitudinal and transverse potentials were simultaneously measured for MoS2 in the Gr/MoS2 device for determining Hall mobility as a function of B, VTG, and VBG at 2 K (Fig. 5a, b). A nearly zero longitudinal potential is clearly observed compared to room temperature (Fig. 3d), indicating enhanced Coulomb drag effect because of the suppressed phonon scattering. The VTG-dependent Hall mobility is almost identical to the field-effect mobility (reaching up to 104 cm2 V−1 s−1 in the Coulomb drag regime) (see Supplementary Note 6). Meanwhile, the field-effect mobility is underestimated by Hall mobility, as the net-oxide capacitance is overestimated by a factor of 3 (Fig. 5c). Another distinct evidence of Coulomb drag phenomenon is the carrier-type conversion in MoS2 of the Gr/MoS2 device. The carrier type and density were determined from Hall measurement with a sweeping magnetic field (Fig. 5c and see Supplementary Fig. 10a and b). The suppressed number and sign reversal of effective carriers in MoS2 at Gr/MoS2 heterointerface were clearly observed around VTG −10 V at VBG = 40 V, clearly implying that the electrons in MoS2 are dragged by the holes in Gr in the p-Gr/n-MoS2 regime.

### Conclusion

We designed and demonstrated Coulomb drag transistors based on Gr/MoS2 heterostructures for achieving high on-/off-current ratio and mobility. Carrier mobility could be enhanced using a hexagonal boron nitride gate insulator38,39 instead of Al2O3 that degrades the carrier mobility of 2D materials (see Supplementary Fig. 9 and Supplementary Note 5). Several issues remain to be resolved for the practical applications of Coulomb drag transistors, such as their contact resistance20,21,22, carrier-type control40, and widening of the operation-voltage window. Nevertheless, our Coulomb drag transistors extend the research fields for dissipation-less devices with 2D heterostructures under ambient conditions.

## Methods

### Graphene growth via chemical vapor deposition (CVD)

To obtain large single-crystal graphene (Gr) flakes, the following procedure was employed. Initially, a Cu foil was preannealed at 1070 °C for 2 h in a H2 and Ar atmosphere to remove organic residues from its surface and improve its crystallinity. Subsequently, one side of the foil was chemically polished, i.e., the Cu surface was etched with an etchant (FeCl3, Taekwang, Korea) and rinsed with deionized (DI) water to obtain a flat and organic residue-free substrate. Before Gr growth, the clean Cu foil was annealed again at 1070 °C for 30 min in the growth chamber to remove any remaining residues on the surface. In the next step, a low concentration CH4 gas (0.1% Ar-based gas) was passed through the chamber. After annealing, the Cu foil was immediately exposed to a flow of 3 sccm CH4, 20 sccm H2 (99.9999%), and 1000 sccm Ar (99.9999%) at the same temperature (1070 °C) for 30 min without exposure to air to synthesize high-quality Gr flakes.

### MoS2 growth via CVD

We synthesized monolayer MoS2 by sulfurizing a solution-based precursor to improve crystal quality41,42. The Mo precursor (12 mM ammonium heptamolybdate in DI water (Sigma-Aldrich, 431346)) and a promoter (10 mM sodium hydroxide in DI water (Sigma-Aldrich, 306576)) were mixed and spin-coated onto a SiO2/Si wafer at 3000 rpm for 1 min. To sulfurize the Mo-based precursor on the substrate, sulfur powder (100 mg) and the prepared substrate were placed in zones 1 and 2 of the growth chamber, respectively, and 500 sccm N2 was passed as a carrier gas during the synthesis process. After a sufficient N2 purging over 1 h, single-crystal MoS2 was synthesized over a period of 15 min at atmospheric pressure in different temperature zones, i.e., zone 1 (210 °C) and zone 2 (780 °C).

### Device fabrication using graphene/MoS2 heterostructure

To transfer each material, we spin-coated polymethylmethacrylate (PMMA, Sigma-Aldrich) onto the substrate along with Gr/MoS2 at 2000 rpm for 1 min. The flexible PMMA film holds the material and minimizes any damage during the transfer process. PMMA-coated MoS2 was separated from the substrate by dipping into DI water and then transferred onto a SiO2 (300 nm)/Si target substrate. In our MoS2 growth conditions, the water-soluble promoter remains near and underneath the MoS2 layer. We removed PMMA by cleaning with acetone, followed by annealing at 350 °C for 2 h in a H2/Ar atmosphere. The annealing process enhanced interaction between MoS2 and SiO2 as well, resulting in a strong adhesion.

To detach PMMA/Gr from the Cu foil, voltage was applied through a Pt wire to the Cu foil in a 0.1 M NaOH solution (water-electrolysis method)43. The effect of chemical doping is largely suppressed by this method, which is a key aspect in enhancing the device performance. To further remove chemical residues, Gr was rinsed several times with DI water. We then transferred and stacked Gr onto the MoS2 flakes on the target substrate. The same cleaning and annealing processes (350 °C for 2 h in H2/Ar) were conducted to remove residual PMMA and facilitate strong interlayer coupling.

Gr/MoS2 devices were fabricated using standard e-beam lithography and metallization with Cr (5 nm)/Au (60 nm). To define the channel area for the six-probe Hall bar structure, MoS2 and Gr were patterned and etched using O2 and SF6 plasma (10 sccm O2 and 20 W for 20 s, followed by 20 sccm SF6 at 10 W for 10 s). Later, Al2O3 (30 nm) was deposited via atomic layer deposition on the Gr/MoS2 device to serve as the top-gate dielectric. The top gate was fabricated by e-beam patterning and Cr (5 nm)/Au (60 nm) deposition to realize a dual-gating device as the final configuration.

### Optical characterization

To identify each material and confirm its interlayer charge-transfer effect, Raman and photoluminescence (PL) measurements were performed on Gr/MoS2 and MoS2 after Al2O3 passivation. To this end, a confocal Raman microscope (NTEGRA Spectra, NT-MDT) equipped with a 532-nm excitation laser and an objective lens (numerical aperture of 0.7) was used.

### Electrical characterizations

Device performance was characterized at each step after annealing at 150 °C for 2 h in high vacuum (10−6 Torr). Measurements were conducted at room temperature using a standard semiconductor characterization system (4200-SCS, Keithley Instruments). To enhance data reliability, we also measured the device performance with another characterization system (B1500A, Keysight Technologies). The temperature- and magnetic field-dependent performances of the devices were monitored under high vacuum (10−7 Torr) in a cryostat (PPMS, Quantum Design, Inc.).