Main

Low-thermal-budget electronics are manufactured on unconventional substrates such as paper, plastic or metal foil1,2. These devices typically use thin-film semiconductors such as organic semiconductors, amorphous oxide semiconductors (AOSs) or amorphous silicon1,2. AOSs, in particular, offer several advantages including affordability, low-temperature fabrication, high carrier mobilities, transparency in the visible spectrum, mechanical flexibility and scalable deposition methods3,4,5,6. AOS-based thin-film transistors (TFTs) have been used in applications ranging from simple logic gates7,8,9 to 32 bit microprocessors10, but the development of AOS-based TFT integrated circuits (ICs) has been limited. This is due to the low resolution and large feature size of current fabrication techniques, which restricts transistor density.

Monolithic three-dimensional (3D) vertically integrated circuits (Mo3D-ICs) could overcome these challenges and improve scaling in AOS IC technology11,12,13,14,15,16. The predominant method for fabricating Mo3D-ICs involves bonding processes that are categorized as wafer-on-wafer, die-on-die and die-on-wafer17. However, this approach faces challenges—including low power density, high-temperature bonding processes and lack of industry standards—that limit their widespread use17.

Recent research has focused on layer-by-layer or additive manufacturing methods, which could provide a more efficient, cost-effective and scalable approach for Mo3D-IC technology. For example, hybrid complementary transistors have been created using solution-processed ZnO and 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (diF-TESADT) channel layers, which can offer balanced electron and hole mobilities11. Alternatively, ZnO nanowire field-effect transistors have been vertically stacked to create nano-floating gate memories and invertors14, and a complex 3D complementary invertor has been fabricated using a vertically stacked p-channel SnO TFT and an n-channel indium gallium zinc oxide TFT13. However, these integrated oxide–semiconductor-based transistors have limitations, including high-temperature processing, low yield and incompatibility with scalable complementary metal–oxide–semiconductor (CMOS) integration.

In this article, we describe a method for manufacturing 3D-integrated metal-oxide transistors and circuits at room temperature that uses established materials and processing technologies. We used the approach to fabricate n-channel In2O3 TFTs on Si/SiO2 substrates with up to ten stacks in a range of architectures. Our devices exhibited field-effect mobilities of up to 15 cm2 V−1 s−1, subthreshold swing of 0.4 V dec−1 and current on/off ratios of up to 108. We also demonstrated unipolar invertors with gains of up to 50 and good noise margins. Although we did not fabricate vertical interconnect accesses for interconnection, we outline potential approaches for their use in our device architecture (Supplementary Section 1). We also discuss potential fabrication methods for creating vertical interconnect accesses that can avoid the use of chemical-mechanical polishing. This approach could reduce the complexity of manufacturing 3D-stacked transistors with interconnections.

Stacked device fabrication

Figure 1a,b shows schematics of bottom-gate (BG) and top-gate (TG) n-channel In2O3 TFTs, which were fabricated on Si/SiO2 substrates. We used parylene C as the buffer and dielectric material due to its excellent insulating properties, facile processing and high conformity. By reconfiguring the vertical and spatial locations of the BG and TG electrodes during stack processing, we could fabricate dual-gate (DG) transistors (Fig. 1c). From Fig. 1a–c, it is evident that our proposed BG, TG and DG devices follow an underlapping transistor architecture. ‘Underlapping’ refers to the absence of an overlap between the gate-source and the gate-drain regions. In Supplementary Section 2, we explain the reason for choosing underlapping over overlapping devices, although the latter architecture has the potential to yield better performance. Our processing methodology allows several layers of functional devices to be processed on top of each other sequentially at near room temperature. Figure 1d shows a schematic representation of the vertically integrated ten-stack (10-S) DG In2O3 transistors.

Fig. 1: 3D monolithic integration of In2O3 TFTs.
figure 1

a–c, Two-dimensional and 3D schematic representations of BG (a), TG (b) and DG (c) transistors. d, 3D schematic representation of 10-S DG transistors on an Si/SiO2 substrate.

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The 10-S configuration consists of ten sequentially processed stacks (S1 to S10) with 72 functional layers: a base Si substrate, an SiO2 insulation layer, 30 metal electrode layers (ten BGs, ten TGs and ten sources/drains), ten In2O3 channels and 30 parylene-C layers (20 gate-dielectric and ten additional buffers). Figure 2a is a camera image of four 10-S devices on an Si/SiO2 substrate (2 cm × 2 cm). Figure 2b–e shows the processing steps and final layout of the 10-S system. In brief, Fig. 2b shows an optical micrograph of the patterned BG aluminium electrode in the first stack (S1). Parylene C (gate dielectric) and In2O3 were deposited using chemical vapour deposition (CVD) and radio-frequency magnetron sputtering, respectively. Next, fabrication of the BG device was completed by forming a metal source and drain (Fig. 2c). Parylene C (gate dielectric) was deposited on top of the BG device using the same CVD process. Finally, the first stack (S1) of the DG device was fabricated by forming an aluminium TG electrode (Fig. 2d). The same fabrication procedure was repeated ten times with interstack buffers (parylene C) to realize the 10-S DG device (Fig. 2e). In Fig. 2e, B1–B10, T1–T10, SC1–SC10 and D1–D10 refer to the BG, TG, source and drain electrodes, respectively, in the ten-layer stack. Details of the fabrication flow for the 10-S devices are provided in Supplementary Table 1. This table also shows the thickness of each layer in the 10-S system. To realize a reliable 10-S system, determining the appropriate thickness of parylene C (which acts as both a dielectric and a buffer) and the gate electrode is crucial. The relevant experimental investigation (Supplementary Figs. 1–6) and an explanation can be found in Supplementary Section 3. After determining the appropriate thicknesses, we recorded the surface roughness of each layer during the fabrication of the 10-S system (Supplementary Section 4 and Supplementary Fig. 7). Figure 2f presents a cross-sectional scanning electron micrograph of the device area covering the source, gate and drain regions. Figure 2g,h shows zoom-in cross-sectional images of the gate-source and gate-drain regions, respectively. Figure 2i is a schematic depicting the cross section of the 10-S device, and Fig. 2j presents cross-sectional transmission electron microscopy and energy-dispersive X-ray spectroscopy (EDX) images of the 10-S system. The latter data confirm the conformal deposition of the 72 layers and the minimal layer interdiffusion required for 3D vertical integration and good device performance.

Fig. 2: Processing steps for fabricating individual TFTs integrated vertically in the 10-S device and its structural and elemental analysis.
figure 2

a, Camera image of as-completed 10-S devices on a silicon substrate. b–d, Micrographs of the different patterning steps used to fabricate the individual TFTs. b, Step 1: Patterning the BG Al electrode. c, Step 2: Patterning the source and drain Al electrodes following the deposition of the gate dielectric (parylene C) and the In2O3 channel layers. d, Step 3: Patterning the final TG Al electrode following the deposition of the TG dielectric (parylene C). e, Micrograph of the final 10-S structure showing the sets of ten metal electrodes: BG (B1–B10), TG (T1–T10), source (S1–S10) and drain (D1–D10) electrodes. f–h, Cross-sectional scanning electron micrograph of 10-S structure (f) with enlarged images of the source-gate region (g) and gate-drain region (h). i, Schematic depiction of the 10-S structure. j, Cross-sectional transmission electron microscopy (left) and EDX analysis of the completed 10-S devices. EDX images show the distribution of Al, C, In and O atoms across the 10-S device.

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Transistor characteristics

Figure 3a shows the transfer curves for BG devices in different layers across the 10-S system. The transfer curves were obtained by sweeping gate-source voltage VGS from −10 V to +5 V at drain-source voltage VDS = +5 V. For both driver and load, the fabricated BG device had channel width W = 500 µm, channel length LCH = 15 µm and gate length Lg = 5 µm. From the transfer curves in Supplementary Fig. 8a, the threshold voltage (VTH) was calculated as being between −0.52 and −1.54 V, confirming the depletion-mode operation. The VTH values calculated from the linear transfer curves (Supplementary Fig. 8a) are summarized in Supplementary Table 2. The output curves in Supplementary Fig. 8b display linear and saturation regimes, respectively. The gate leakage for all devices was low, ~10−11 A, suggesting that a good quality dielectric layer had formed across the 10-S system (Supplementary Fig. 8c). Based on these data, we concluded that all the BG devices exhibited identical depletion-mode characteristics, with good reproducibility across the vertically integrated 10-S system. Other transistor parameters, including the electron field-effect mobility (µFE), subthreshold swing (SS), current ratio (ION/IOFF), and transconductance (GM), were also calculated from the transfer and output characteristics (Methods). The error bars of the transistor parameters were calculated from devices fabricated on three different chips, each containing four 10-S systems (Fig. 2a). The transistors show modest fluctuations of µFE ranging from 1.05 to 2.65 cm2 V−1 s−1 (Fig. 3b). The µFE values calculated using equation (2) are summarized in Supplementary Table 2. The ION/IOFF ratio of the In2O3 TFTs in the 10-S system was calculated using equation (1) to be ~106 (Fig. 3c). As seen in Fig. 3c, in the 10-S system, stacks S8, S9 and S10 had poor current ratios. The ensuing BG TFTs had a high SS value of 1–2 V dec−1 (Supplementary Fig. 8d), which were calculated using equation (3). From the transfer curves (Fig. 3a), GM was calculated to be ~8.51 µS (Supplementary Table 3). The measured values of the accumulation capacitance (CACC) used to calculate µFE are listed in Supplementary Table 3. These tabulated CACC values were obtained from the characteristics of a metal–oxide–semiconductor capacitor (MOSCAP; Supplementary Fig. 9).

Fig. 3: Device characteristics.
figure 3

a–c, Transfer (a), mobility (b) and current ratio (c) of 10-S BG devices. d–f, Transfer (d), mobility (e) and current ratio (f) of 10-S TG devices. g–i, Transfer (g), mobility (h) and current ratio (i) of 10-S DG devices. For both the driver and load, the channel width W = 500 µm, channel length LCH = 15 µm and gate length Lg = 5 µm. We fabricated three chips, each containing four 10-S devices, resulting in a total sample size N = 12 transistors. The error bars for the transistor parameters were calculated for the four devices in each chip. Statistical information for both the mobility and current ratio is provided within the corresponding bar graphs.

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Figure 3d displays the transfer curves of TG In2O3 TFTs in the 10-S system measured at VDS = 5 V. For both driver and load, the fabricated TG device had channel width W = 500 µm, channel length LCH = 15 µm and gate length Lg = 5 µm. Unlike transistors based on the BG architecture, the TG devices had a more negative VTH with values ranging between −5 and −6 V (Supplementary Fig. 10a). Supplementary Table 2 summarizes the VTH of all the TG devices integrated vertically in the 10-S system. The gate-leakage current (IG) for all TG devices was low, ~10−12 A (Supplementary Fig. 10c) and highlights the good quality of the parylene-C layer that acts as both the buffer and dielectric. The electron µFE ranged between 0.5 to 1.13 cm2 V−1 s−1 (Supplementary Table 2 and Fig. 3e). Both the BG and TG architectures exhibited modest µFE with relatively small variations between different batches (Supplementary Table 2). We attribute these to the non-uniformities in the semiconductor/channel interface during sequential growth. These structural variations are evident in the cross-sectional transmission electron microscopy and EDX analysis of the 10-S system shown in Fig. 2. The ION/IOFF ratio of TG devices was one order of magnitude smaller than that of the BG transistors, which we attributed to the increased off current (Fig. 3f). Supplementary Fig. 10d displays the SS values for the TG TFTs, which are slightly higher than those of the BG devices (Supplementary Fig. 8d), indicating a lower-quality parylene-C/In2O3 channel interface, which ultimately resulted in a lower µFE. Notably, both device architectures had low IG, which highlights the excellent insulating nature of the parylene-C interlayers across the vertically integrated 10-S system. The CACC used to calculate µFE for the TG devices was obtained from the MOSCAP characteristics in Supplementary Fig. 11 with the derived values tabulated in Supplementary Table 3. The MOSCAPs had clear accumulation and depletion regions from which CACC was extracted.

To improve the operating characteristics of the vertically integrated In2O3 TFTs, we developed DG devices using parylene C as the bottom and top dielectric layers (Fig. 1c). For both driver and load, the fabricated DG device had channel width W = 500 µm, channel length LCH = 15 µm and gate length Lg = 5 µm. Figure 3g shows the transfer characteristics of the ten vertically integrated DG transistors measured at VDS = 5 V. The VTH values were calculated from the transfer curves in Supplementary Fig. 12a and are summarized in Supplementary Table 2. Values are between 0.31 and −2.12 V. The saturation currents observed in the output curves (Supplementary Fig. 12b) are consistent with the transfer characteristics (Supplementary Fig. 12a). The IG for the DG devices remained low, of the order of ~10−12 A (Supplementary Fig. 12c). Compared to single-gate transistors, the DG In2O3 TFTs had a higher µFE ≈ 15 cm2 V−1 s−1 (Fig. 3h). We attribute this to the high GM, lower CACC and the excellent gate-field coupling to the channel, in agreement with results in the literature11,18. Due to the increased GM and reduced IOFF, the ION/IOFF ratio for the DG devices was remarkably higher, reaching up to ~108 (Fig. 3i). Owing to the improved gate control and the higher GM, the SS of the DG devices was significantly lower, ~0.4 V dec−1 (Supplementary Fig. 12d), compared to single-gate TFTs (Supplementary Figs. 8d and 10d). Moreover, the small variation in the transistor parameters shown in Fig. 3g–i highlights the enhanced device reliability and robustness for developing 3D ICs. The GM and CACC values for the DG devices were calculated from the MOSCAP characteristics in Supplementary Fig. 13 and are presented in Supplementary Table 3.

Device reliability

To validate the reproducibility of our proposed 10-S system, we performed reliability, transient and long-term stability studies on 100 BG, 100 TG and 100 DG devices. The experimental results are in Supplementary Figs. 14–19 and corresponding explanations can be found in Supplementary Section 5. Overall, compared to BG and TG devices, the DG devices demonstrated better reliability and stability characteristics. Consequently, as explained in Supplementary Section 6 (Supplementary Figs. 20 and 21), we tested the bias stress stability, including negative-bias stress and negative-bias temperature stress for 10-S DG devices. Supplementary Fig. 22 illustrates the thermal stability of these 10-S DG transistors. All transistors in the ten stacks exhibited decent thermal stability until 50 °C. However, when the table temperature was increased above 75 °C, all the stacked transistors under test underwent significant negative shifts in the threshold voltage. This confirms their poor thermal stability, which is attributed to the low thermal processing conditions of the layers used in manufacturing 10-S transistors. Improvements in thermal stability could be achieved by optimizing the growth conditions of active layers and the thermal annealing process5,6,19,20. We also observed significant device-to-device variations in the electrical characteristics of 10-S BG, TG and DG devices. These fluctuations may be attributed to the mechanical, electrical or thermal parameters. Corresponding detailed discussions supported by relevant experimental results can be found in ‘Device-to-device variations’ in Supplementary Section 6. In addition to the reliability and stability measurements, we also fabricated and characterized BG, TG and DG transistors with W = 1 µm, Lg = 100 nm and Lch = 500 nm to explore the potential for scaling down the transistors. The experimental results are in Supplementary Fig. 23 and relevant explanations in Supplementary Section 6.

Invertor characteristics

Next, we set out to fabricate NMOS invertor circuits to demonstrate the potential of the 10-S vertically integrated In2O3 TFTs. It is important to note that a typical NMOS invertor circuit comprises two n-type transistors, one acting as the driver and the other as the load. Unlike conventional laterally (two-dimensional) integrated invertors, we used two vertically stacked transistors from the 10-S system in the invertor test. Based on the layer thickness (Supplementary Table 1) and the 10-S architecture, it is evident that the separation between two adjacent stacks is just a 50 nm parylene-C buffer layer. To realize reliable invertor circuits in the 10-S system, understanding the electrical interference or electrical decoupling between the two adjacent stacks is essential. Therefore, we performed an interstack decoupling analysis. The experimental results are in Supplementary Figs. 24 and 25, and a description related to this decoupling analysis is presented in Supplementary Section 7. Figure 4a shows the completed 10-S chip mounted on a printed circuit board (PCB). Symbolic representations of In2O3 TFTs with the TG, BG or DG shorted and a floating DG are shown in Supplementary Fig. 26a–d, respectively. Owing to their superior operating characteristics, we chose DG devices to build the invertor circuit shown in Fig. 4b. Ninety combinations of depletion-load invertor configurations were tested. The biasing conditions used to test the invertor were input voltage VIN = −5 to 5 V and supply voltage VDD = +15 V. Figure 4c shows the invertor voltage-transfer characteristics (VTC) of the first nine combinations out of the 90 tested. The DG device in stack S1 was the driver, and the other devices (S2–S10) were the depletion load. The invertor trip voltage (VTrip), which is the voltage at which the output of the gate transitions from high to low, was approximately −2.2 V, consistent with the VTH of the driver device. Figure 4d shows the gain of the invertor circuits tested. The gain reached a maximum of 47 V/V, which is on par with previously reported 3D-stacked circuits12,13,14,11,18,21,22,23,24. A summary of the VTC and gain characteristics for the remaining 81 invertors featuring different drivers and load TFTs are presented in Supplementary Figs. 27–29. The gain values obtained from the 90 invertor circuits are summarized in Supplementary Table 4. Although not optimal, the VTCs of the invertors were very similar, which demonstrates the reliability of our 3D integration process. From all the cases tested, it is evident that the switching voltage in the VTC curves was negative, which may be attributed to the load transistor being weaker than the driver. To investigate this, we connected different numbers of loads in parallel to observe their influence on the invertor VTC curves. The corresponding experimental outcomes can be found in Supplementary Section 8 and Supplementary Fig. 30. Further tuning of the device geometry and invertor circuitry may enhance performance.

Fig. 4: Circuitry and operating characteristics of the voltage invertors fabricated using the vertically integrated In2O3 TFTs.
figure 4

a, Camera image of the 10-S devices mounted on a PCB. b, Circuitry of the voltage invertor realized using two DG transistors in different layers (S1, S2, S3, …) in the 10-S structure. c, VTCs of nine different invertors measured at VDD = 15 V. d, Signal gain calculated from the VTCs in c. For both the driver and load, the channel width W = 500 µm, channel length LCH = 15 µm and gate length Lg = 5 µm.

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An important advantage of the DG transistor architecture is that it facilitates various connection configurations that may lead to increased speed, lower power dissipation and improved noise immunity compared to conventional single-gate transistors25. For example, the two gate terminals can be shorted (gate-shorted configuration), left floating (gate-floating configuration) or biased at different potentials. By doing so, different switching characteristics can be achieved for the same device. To explore this advantage, we studied the effect of a fixed TG bias on the operating characteristics of a DG vertically integrated transistor. We achieved this by sweeping the BG potential (VBG) while maintaining the TG potential (VTG1) at a fixed bias. VTG1 was subjected to different biasing conditions, namely 10, 5, 0, −5, or −10 V. The measured transfer curves for representative DG In2O3 TFTs within a 10-S system are shown in Supplementary Fig. 31 and Fig. 5a–c. All transfer curves were obtained at VDS = 5 V while sweeping VBG between −10 and 15 V. For VTG1 = 10 V (Fig. 5a), the positive bias enabled more electrons to accumulate due to a synergistic effect, which shifted ON voltage VON towards more negative voltages (« −10 V). In this case, the voltage range applied to VBG was insufficient to fully deplete the accumulated electrons in the channel. A stepwise reduction of VTG1 from 10 V to eventually −10 V led to a gradual shift of VON towards more positive voltages and it reached −7.5 V (Supplementary Fig. 31b), −3 V (Figs. 5b), 1.5 V (Supplementary Fig. 31c) and 5.5 V (Fig. 5c) for VTG1 = 5, 0, −5 and −10 V, respectively. Figure 5d illustrates the shift in VON measured from the transfer characteristics of the ten stacks (S1 to S10) under different VTG1 bias conditions ranging from 10 to −10 V. This tunable behaviour indicates that fewer electrons accumulated in the channel. The concentration of these electrons can be effectively tuned with VBG. These results highlight the ability of the DG architecture to fine-tune the operating characteristics of TFTs at different levels in the vertically integrated 10-S. The layout of each gate electrode in the 10-S system can be designed to act as a dedicated gate for a single TFT or as a shared/common gate for two transistors in neighbouring stacks (S1 and S2). This unique feature makes the vertically integrated 10-S system highly reconfigurable, potentially delivering ultra-high-density integrated circuits.

Fig. 5: Configurable characteristics of the invertor circuit.
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a–c, Transfer curves for 3D-stacked transistors (S1–S10) for different VTG1 values: +10 V (a), 0 V (b) and −10 V (c). VBG and VTG1 are for the BG and TG terminals of the driver device. VTG2 is for the TG terminal of the load device. d, VON values measured from the transfer characteristics of the ten stacks (S1 to S10) for different VTG1 bias conditions (10 to −10 V). e,f, Invertor current (e) and VTC characteristics (f) of the optimized circuit operating at VTG1 = −10 V and tested for VTG2 = +10 and −10 V. The dotted lines in f are the gain characteristics. g, Overview of the wide range over which VTrip can be adjusted for VTG1 and VTG2 biases between −10 and + 10 V. VTrip is the trip voltage where the peak gain occurs. h, This graph highlights the operating region of the VTrip tunable characteristics in g. i, Noise margin low (NML) and noise margin high (NMH) were calculated for invertors operating at VTG1 = −10 and −5 V, and tested for VTG2 = +10 and −10 V.

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To demonstrate how the DG architecture can be used to fine-tune the operating characteristics of unipolar invertors, we integrated two In2O3 TFTs, one acting as the load and the other as the driver (Supplementary Fig. 31a). The TG control terminal biases for the driver and load device are VTG1 and VTG2, respectively. The driver transistor was in the S1 layer, whereas the load was in the S2 layer. The invertor output curves, current behaviour and gain characteristics of each invertor measured at fixed VTG1 and VTG2 voltages (10, 5, 0 and −5 V) are presented in Supplementary Fig. 32. VTCs measured at VDD = 15 V with VTG1 = 10 V (Supplementary Fig. 32a) and VTG1 = 5 V (Supplementary Fig. 32d) show unbalanced characteristics with VTrip ≈ −7 V (Supplementary Fig. 32b) and −3 V (Supplementary Fig. 32e), respectively, and a maximum signal gain of around 10 V/V. Further reducing VTG1 to 0 V (Supplementary Fig. 32g) and −5 V (Supplementary Fig. 32j) shifted the VTCs towards more positive voltages with a VTrip of ~2.5 V (Supplementary Fig. 32h) and ~3 V (Supplementary Fig. 32k), respectively, while maintaining the signal gain of ~10. Finally, setting VTG1 = −10 V shifted the VTCs further towards positive potentials with an excellent rail-to-rail output voltage (VOUT) swing. Figure 5e shows the invertor current characteristics for VTG1 = −10 V. The VTrip (Fig. 5f) of this optimized circuit can be precisely tuned from 5.0 to 7.3 V by changing the VTG2 bias from 10 to −10 V with no major change in the signal gain characteristics. Notably, when both VTG1 and VTG2 were set to −10 V, VTrip for the invertor circuit (~7.3 V) was close to VDD/2, showing that the circuit configuration was optimized. The wide range over which VTrip can be adjusted depending on the selection of VTG1 and VTG2 is shown in Fig. 5g. Among the different tunable invertor configurations, those operating at VTG1 = −10, −5 and 0 V had positive VTrip voltages, as seen in Fig. 5g. Invertors with positive VTrip values had a proper working operation region, as depicted in Fig. 5h. The VTrip values for invertor configurations operating at VTG1 = −10 and −5 V are close to VDD/2 (Fig. 5h), suggesting that they had better noise margins compared to the other invertor configurations tested. For these two configurations, we calculated the noise margin low and noise margin high, as shown in Fig. 5i. These results show the special capability of the double-gate architecture to precisely adjust the operating characteristics of the transistors and the ensuing logic circuits. Combined with the 3D-integrated 10-S arrangement and the configurability of the system, this could be a beneficial technology and lead to new avenues of research.

Conclusions

We have described an approach for monolithic 3D TFT integration at room temperature, which can be used to stack ten vertical layers. Figure 6 compares our work with other 3D-integrated TFT demonstrations. Our devices offer encouraging performance characteristics, including a low subthreshold swing (0.4 V dec−1), high channel current on/off ratio (108) and high field-effect electron mobility (15 cm2 V−1 s−1) across the stack. We used DG transistors at different levels in the stack to create configurable logic invertors that exhibit tunable operating characteristics with signal gains of up to 50 V/V. Our results illustrate the scalability and strong performance of our 3D monolithic vertical integration approach and provide a potential route to cheaper and highly scalable large-area electronics.

Fig. 6: Benchmark graph.
figure 6

Comparison of In2O3 in this work with reported state-of-the-art values in the literature based on various factors such as the number of vertical stacks, transistor mobility and processing temperature. IGZO, indium gallium zinc oxide. TU-3, 4,8-bis[5-(3-cyanophenyl)thiophene-2-yl] benzo[1,2-c:4,5-c′]bis[1,2,5]thiadiazole; DNTT, dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene.

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Methods

Transistor fabrication

A thick 2 µm layer of SiO2 was thermally grown on a highly doped p-type Si substrate (Si/SiO2). This Si/SiO2 substrate was subjected to a standard cleaning procedure using acetone, isopropyl alcohol and deionized water for 5 min each. Fabrication of the first stack S1 of the DG device was started by d.c. sputtering and lithography patterning a 20-nm-thick BG aluminium (Al) electrode onto the Si/SiO2 substrate. A 25-nm-thick layer of parylene C as the BG dielectric was deposited at room temperature on top of the Al electrode using a specialized CVD coating system. After that, around a 10 nm In2O3 active channel layer was deposited at room temperature using a radio-frequency sputtering system. The sputtering conditions (100 W, 20 standard cubic centimetres per minute (sccm) Ar and 20 sccm O2 flow at 10 mTorr pressure) were optimized to deposit the active channel layer. Then, the source and drain Al electrodes were patterned on top of the active channel layer. Next, a 25 nm parylene-C TG dielectric was deposited at room temperature using the same specialized CVD coating system. Finally, the first stack DG device was fabricated by d.c. sputtering the TG Al electrode. The same fabrication process used for the S1 stack was repeated nine more times to complete the 3D monolithic integration of the ten stacks (S1–10). A 25 nm layer of parylene C was used as the buffer between each stack. The 10-S devices have 72 functional layers: a base Si substrate, a SiO2 insulation layer, 30 metal electrode layers (ten BGs, ten TGs and ten sources/drains), ten In2O3 channels and 30 parylene-C layers (20 gate-dielectric and ten buffers). Supplementary Table 1 summarizes the fabrication flow for all 72 layers used in this integration process.

Transistor characterization

Electrical characterization under ambient air was measured using a Keithley 4200 semiconductor parameter analyser. In this study, transistor parameters, such as field-effect mobility (µFE), subthreshold swing (SS), current ratio (ION/IOFF) and transconductance (GM), were calculated using the transfer curves obtained. The equations used to calculate µFE, SS and ION/IOFF are as follows:

$$I_{{\rm{ON}}}/I_{{\rm{OFF}}}=\frac{{I}_\mathrm{D,{OFF}}}{{I}_\mathrm{D,{SAT}}},$$
(1)
$$\mu_{{\rm{FE}}}=\frac{L}{WC_{i}}\,\frac{\partial {I}_\mathrm{D,{lin}}}{\partial {V}_\mathrm{G}}$$
(2)
$$\begin{array}{l}C_{{\rm{i}}}=\frac{{C}_{\mathrm{ACC}}}{WL},\\ {\rm{SS}}=\frac{\partial({\log}_{10}I_{\mathrm{D}})}{\partial {V}_{\mathrm{G}}}-1,\end{array}$$
(3)

where L is the channel length, W the channel width, Ci the dielectric capacitance (F cm−2), CACC the dielectric accumulation capacitance (F), ID,lin the drain current from the linear region, VG the gate voltage, ID,OFF the drain current from the transistor off region and ID,SAT the drain current from the transistor saturation region.

Wire-bonding technique for testing chips

To attach our chips to the PCB, we used an aluminium wire-bonding machine from WeiChen, as shown in Supplementary Fig. 33a. This machine uses ultrasonic waves between the needle tip and the surface of the sample to attach Al wires. This way, we can connect the metal parts of our chip, like the gate, source and drain of the ten stacks, to the Al pads on the PCB.

Supplementary Fig. 33b shows the first and second bonding steps, which are the two ends of the wire. In our case, one end is on the chip’s metal pads, and the other is on the PCB’s pads. To bond wires successfully, we can adjust the machine’s settings like power (Supplementary Fig. 33b), time (Supplementary Fig. 33b) and pressure (Supplementary Fig. 33c). These settings were set by the manufacturer for a smooth process and work for Au, Al and Cu pads. If we need to bond different metals, we might have to experiment to find the right settings. We used Al wire (Supplementary Fig. 33d) for our devices. After wire bonding, we could then measure the device and circuit characteristics of these chips.