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Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses

Nature Electronics volume 7, pages 662–670 (2024)Cite this article

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Abstract

Integrating thin atomic-layer-deposited dielectrics with two-dimensional (2D) semiconductors could be used to fabricate 2D transistors with sub-1 nm capacitance-equivalent thicknesses. However, non-uniform nucleation from atomic-layer deposition on inert surfaces and subsequent high-energy metal evaporation can make atomically thin dielectrics non-insulating. Here, we report a bismuth-oxide-assisted chemical vapour deposition method to synthesize single-crystalline metal nanosheets with atomically flat surfaces. The nanosheets grow vertically on a substrate and can be easily transferred to a target substrate through polymer-free mechanical pressing. We show that palladium nanosheets offer an excellent surface for atomic-layer deposition of flat aluminium oxide (Al2O3) and hafnium oxide (HfO2) dielectrics with sub-3 nm thicknesses. These can then be laminated onto few-layer molybdenum disulfide (MoS2) as a gate stack with a capacitance-equivalent thickness of 0.9 nm and a capacitance density of around 3.9 μF cm−2. Our MoS2 top-gated transistors with a 2-nm-thick Al2O3 or HfO2 dielectric exhibit leakage currents of 10−6 A cm−2, low operating voltages of around 0.45 V and a hysteresis of less than 1 mV.

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Fig. 1: CVD growth, polymer-free transfer and characterizations of vertically grown single-crystalline metals.
Fig. 2: ALD compatibility and vdW integration of vertically grown Pd nanosheets.
Fig. 3: MoS2 transistors with sub-3 nm Al2O3/Pd as top-gate dielectric and electrode.
Fig. 4: MoS2 transistors with 2 nm HfO2/Pd based as top-gate dielectric and electrode.

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The data that support the findings of this study are available from the corresponding authors upon reasonable request.

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Acknowledgements

J.W. acknowledges financial support from the National Natural Science Foundation of China (grant no. 92064005)) and the Opening Project of State Key Laboratory of High Performance Ceramics and Superfine Microstructure (grant no. SKL202211SIC). F.L. acknowledges financial support from National key research and development program of China (grant no. 2021YFA1601004).

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Authors and Affiliations

  1. Tianjin Key Laboratory for Rare Earth Materials and Applications, Center for Rare Earth and Inorganic Functional Materials, Smart Sensor Interdisciplinary Science Center, School of Materials Science and Engineering, Nankai University, Tianjin, China

    Lei Zhang, Zhaochao Liu, Wei Ai, Jiabiao Chen, Zunxian Lv, Bing Wang, Mingjian Yang, Feng Luo & Jinxiong Wu

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  1. Lei Zhang
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Contributions

J.W. convinced the original ideas and supervised the whole project. L.Z. performed the CVD growth, characterization, device fabrication and electrical measurements under the assistance of Z. Liu, W.A., J.C. Z. Lv, B.W. and M.Y. The paper was written by J.W. and L.Z. with input from other authors. F.L. cosupervised the whole project and gave constructive suggestions. All authors contributed to the scientific discussions.

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Correspondence to Jinxiong Wu.

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Nature Electronics thanks Yanyu Jia and Yury Illarionov for their contribution to the peer review of this work.

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Supplementary Figs. 1–24 and Table 1.

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Zhang, L., Liu, Z., Ai, W. et al. Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses. Nat Electron 7, 662–670 (2024). https://doi.org/10.1038/s41928-024-01202-3

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