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A large-scale integrated vector–matrix multiplication processor based on monolayer molybdenum disulfide memories


Data-driven algorithms—such as signal processing and artificial neural networks—are required to process and extract meaningful information from the massive amounts of data currently being produced in the world. This processing is, however, limited by the traditional von Neumann architecture with its physical separation of processing and memory, which motivates the development of in-memory computing. Here we report an integrated 32 × 32 vector–matrix multiplier with 1,024 floating-gate field-effect transistors that use monolayer molybdenum disulfide as the channel material. In our wafer-scale fabrication process, we achieve a high yield and low device-to-device variability, which are prerequisites for practical applications. A statistical analysis highlights the potential for multilevel and analogue storage with a single programming pulse, allowing our accelerator to be programmed using an efficient open-loop programming scheme. We also demonstrate reliable, discrete signal processing in a parallel manner.

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Fig. 1: Device and matrix description and characterization.
Fig. 2: Open-loop programming.
Fig. 3: MAC operations.
Fig. 4: Signal processing based on in-memory processing.

Data availability

The data that support the findings of this study are available via Zenodo at


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We thank Z. Benes (CMI) for help with the electron-beam lithography and R. Chiesa for assistance with the energy-dispersive X-ray measurements. Device preparation was carried out in the EPFL Centre of MicroNanotechnology (CMI). We thank B. Bartova and R. Therisod (CIME) for device cross-sectioning and transmission electron microscopy imaging, which were carried out at the EPFL Interdisciplinary Centre for Electron Microscopy (CIME). We acknowledge support from the European Union’s Horizon 2020 research and innovation programme under grant agreement nos. 829035 QUEFORMAL (to G.M.M., Z.W. and A.K.), 785219 and 881603 (Graphene Flagship Core 2 and Core 3) to A.K. and 964735 (EXTREME-IR) to H.J and A.K.; the European Research Council (ERC, grant nos. 682332 and 899775, to H.J., M.T. and A.K.); the CCMX Materials Challenge grant ‘Large area growth of 2D materials for device integration’ (to A.R. and A.K.); and the Swiss National Science Foundation (grant no. 175822, to G.P. and A.K.).

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Authors and Affiliations



A.K. initiated and supervised the project. G.M.M. fabricated the devices, designed/prepared the measurement setup and performed the device characterization and remaining measurements. H.J. and Z.W. grew the 2D materials and assisted in materials characterization under the supervision of A.R. M.T. performed the high-resolution transmission electron microscopy for the characterization of devices and materials. G.P. performed the atomic force microscopy imaging and elemental characterization. A.K. and G.M.M. analysed the data. The manuscript was written by G.M.M. and A.K. with input from all authors.

Corresponding author

Correspondence to Andras Kis.

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Nature Electronics thanks Su-Ting Han, Jing-Kai Huang and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary Figs. 1–22 and Sections 1–7.

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Migliato Marega, G., Ji, H.G., Wang, Z. et al. A large-scale integrated vector–matrix multiplication processor based on monolayer molybdenum disulfide memories. Nat Electron (2023).

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