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An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture


Quantum-inspired computing systems can be used to efficiently solve combinatorial optimization problems. In developing such systems, a key challenge is the creation of large hardware topologies with all-to-all node connectivity that allow arbitrary problem graphs to be directly mapped to the hardware. Here we report a physics-based Ising solver chip fabricated in a standard 1.2 V, 65 nm complementary metal–oxide–semiconductor technology. The chip features an all-to-all architecture with 48 spins and a highly uniform coupling circuit with integer weights ranging from −14 to +14. The all-to-all architecture strongly couples a horizontal oscillator with a vertical oscillator so that each horizontal–vertical oscillator pair intersects with all the other pairs in a crossbar-style array and allows any graph with up to 48 nodes to be directly mapped to the hardware. We use the Ising solver chip to carry out statistical measurements for different problem sizes, graph densities, operating temperatures and problem instances.

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Fig. 1: Ising solver compute flow, connectivity comparison table and minor embedding examples.
Fig. 2: Proposed all-to-all array architecture and chip layout.
Fig. 3: Proposed multibit coupling-weight circuit and weight configurations.
Fig. 4: Statistical data collected from the all-to-all Ising solver chip.
Fig. 5: Number of spins and coupling-weight resolution can be dynamically reconfigured by software.

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Data availability

Graph data/problem sets and test data presented in this paper are available via figshare at data are provided with this paper.

Code availability

The testing program used to compare the Ising chip solutions with the qbsolv 0.3.4. software solutions is available via figshare at


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This work was supported in part by the DARPA Quantum-inspired Classical Computing (QuICC) program under AFRL contract FA8750-22-C-1034. H.L. was supported in part by the University of Minnesota College of Science and Engineering Graduate Fellowship.

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Authors and Affiliations



H.L., W.M. and C.H.K. collaborated on the circuit and architecture designs of the integrated circuit. H.L. and H.Y. were responsible for creating the layout for the fabrication process. H.L. led the testing and characterization of the chip, whereas H.L., W.M., S.S. and C.H.K. jointly analysed the test data. The paper was primarily authored by H.L. and C.H.K., with W.M. and S.S. contributing to its editing and revision.

Corresponding author

Correspondence to Chris H. Kim.

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Competing interests

The authors declare the following competing interest: US patent application no. 17/975,825 (Circuit having fully connected ring oscillators).

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Nature Electronics thanks Kazushi Kawamura, Dmitri Nikonov, and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Lo, H., Moy, W., Yu, H. et al. An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture. Nat Electron 6, 771–778 (2023).

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