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Wafer-scale transistor arrays fabricated using slot-die printing of molybdenum disulfide and sodium-embedded alumina


Two-dimensional materials made via solution processing could be used to create next-generation electronic devices at scale. However, existing solution processing methods typically have a trade-off between scalability and material quality, which makes them unsuitable for practical applications. Here we show that wafer-scale arrays of molybdenum-disulfide-based transistors can be fabricated using a commercial slot-die printing process. We create inks of molybdenum disulfide nanosheets and sodium-embedded alumina for printing of the semiconductor and gate dielectric layer, respectively. The transistors exhibit average charge carrier mobilities of 80.0 cm2 V−1 s−1 in field-effect transistor measurements and 132.9 cm2 V−1 s−1 in Hall measurements at room temperature. The high charge carrier mobility is attributed to the sodium-embedded alumina gate dielectric, which causes a band-like charge carrier transport in the molybdenum-disulfide-nanosheet-based thin-film networks. We use the transistors to create various logic gates, including NOT, NOR, NAND and static random-access memory.

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Fig. 1: Device fabrication based on slot-die coating.
Fig. 2: Device optimization and origin of high carrier mobility.
Fig. 3: Applicability to large-area logic circuits.

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Source data are provided with this paper. The other data that support the findings of this study are available from the corresponding authors upon reasonable request.


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This work was supported by the Basic Science Program (NRF-2020R1A2C2007819) through the National Research Foundation (NRF) of Korea funded by the Ministry of Science and ICT, Korea (J.H.C); the Creative Materials Discovery Program through the NRF funded by the Ministry of Science and ICT (NRF-2019M3D1A1078299) (J.H.C.); the Yonsei Signature Research Cluster Program of 2021 (J.H.C.); the NRF grant funded by the Korean Government (MSIT) (RS-2023-00208538) (J. Kang); and the Korea Basic Science Institute (KBSI) National Research Facilities and Equipment Center (NFEC) grant funded by the Korean Government (Ministry of Education) (2019R1A6C1010031) (J. Kang). This research was partially supported by BrainLink program funded by the Ministry of Science and ICT through the NRF of Korea (RS-2023-00237308) (J.H.C. and J. Kang).

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Authors and Affiliations



J.H.C. and J. Kang initiated and supervised all the research. Y.A.K. and Jihyun Kim carried out and designed most of the experimental work and data analysis. M.S.K., D.G.R., D.R. and D.W.K. assisted in the materials processing. S.B.J., Y.S., B.K., D.K. and Jeongmin Kim assisted in the electrical measurements and analysis. All authors discussed the results and contributed to the writing of the manuscript.

Corresponding authors

Correspondence to Joohoon Kang or Jeong Ho Cho.

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Supplementary Figs. 1–29 and Table 1.

Supplementary Video 1

Video showing the slot-die coating process.

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Source data for Fig. 1.

Source Data Fig. 2

Source data for Fig. 2.

Source Data Fig. 3

Source data for Fig. 3.

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Kwon, Y.A., Kim, J., Jo, S.B. et al. Wafer-scale transistor arrays fabricated using slot-die printing of molybdenum disulfide and sodium-embedded alumina. Nat Electron 6, 443–450 (2023).

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