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CMOS-compatible electrochemical synaptic transistor arrays for deep learning accelerators

Nature Electronics volume 6, pages 292–300 (2023)Cite this article

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Abstract

In-memory computing architectures based on memristive crossbar arrays could offer higher computing efficiency than traditional hardware in deep learning applications. However, the core memory devices must be capable of performing high-speed and symmetric analogue programming with small variability. They should also be compatible with silicon technology and scalable to nanometre-sized footprints. Here we report an electrochemical synaptic transistor that operates by shuffling protons between a hydrogenated tungsten oxide channel and gate through a zirconium dioxide protonic electrolyte. These devices offer multistate and symmetric programming of channel conductance via gate-voltage pulse control and small cycle-to-cycle variation. They can be programmed at frequencies approaching the megahertz range and exhibit endurances of over 100 million read–write cycles. They are also compatible with complementary metal–oxide–semiconductor technology and can be scaled to lateral dimensions of 150 × 150 nm2. Through monolithic integration with silicon transistors, we show that pseudo-crossbar arrays can be created for area- and energy-efficient deep learning accelerator applications.

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Fig. 1: Structure and electrical characteristics of CMOS-compatible, all-inorganic protonic ECRAMs.
Fig. 2: Speed, scaling and endurance of CMOS-compatible, all-inorganic protonic ECRAMs.
Fig. 3: Monolithic integration of protonic ECRAMs with silicon transistors to form pseudo-crossbar arrays as in-memory computing accelerators.

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The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work was supported by the US National Science Foundation grant 1950182 (Q.C.) and 2139185 (Q.C. and J.-M.Z.). Substantial aspects of the material characterizations and device fabrications were performed using the shared user facilities of the University of Illinois Fredrick Seitz Materials Research Laboratory and Holonyak Micro and Nanotechnology Laboratory. This work also made use of the Illinois Campus Cluster HAL, utilized resources supported by the National Science Foundation’s Major Research Instrumentation program grant 1725729 and the University of Illinois Urbana-Champaign. We thank T. Spila for assistance with the Rutherford backscattering spectrometry and SIMS measurements, and J. Baltrus for performing the X-ray photoelectron spectroscopy measurements.

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Authors and Affiliations

  1. Department of Materials Science and Engineering, University of Illinois Urbana-Champaign, Urbana, IL, USA

    Jinsong Cui, Fufei An, Jiangchao Qian, Yuxuan Wu, Luke L. Sloan, Saran Pidaparthy, Jian-Min Zuo & Qing Cao

  2. Fredrick Seitz Materials Research Laboratory, University of Illinois Urbana-Champaign, Urbana, IL, USA

    Jian-Min Zuo & Qing Cao

  3. Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, Urbana, IL, USA

    Qing Cao

  4. Department of Chemistry, University of Illinois Urbana-Champaign, Urbana, IL, USA

    Qing Cao

  5. Holonyak Micro and Nanotechnology Laboratory, University of Illinois Urbana-Champaign, Urbana, IL, USA

    Qing Cao

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  1. Jinsong Cui
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Contributions

Q.C. conceived and designed the experiments. J.C., F.A., Y.W. and L.L.S. performed the experiments. J.Q., S.P. and J.-M.Z. performed the STEM-EDS analysis. Q.C. and J.C. wrote the paper. All the authors discussed the results (all of which are reported in the main text and Supplementary Information) and commented on the paper.

Corresponding author

Correspondence to Qing Cao.

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Competing interests

J.-S.C. and Q.C. are inventors on a provisional patent application entitled ‘Solid-state electrochemical random access memory (ECRAM) and methods of making and operating a solid-state ECRAM’ (US 63/434,627) submitted by the Board of Trustees of the University of Illinois.

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Nature Electronics thanks Junwoo Son, Sanghyeon Kim and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 ECRAM fabrication flow.

Schematics illustrating the process flow to fabricate the CMOS-compatible, all-inorganic protonic ECRAM.

Extended Data Fig. 2 All-inorganic protonic ECRAM with elemental metal gate.

a, Schematic of the protonic ECRAM employing only Cr/Au as the gate electrode. b, Symmetric programing of the device channel conductance under gate-current pulses (100 potentiation then 100 depression pulses with the gate-current pulse amplitude of 100 pA and width of 3 s). c, Asymmetric programing of the same device but under gate-voltage pulses (50 potentiation then 50 depression pulses with the gate-voltage pulse amplitude of ±4 V and width of 3 s), caused by the non-zero built-in open-circuit potential.

Extended Data Fig. 3 Read noise and cycle-to-cycle variability of ECRAM operated with 10 µsec programming gate-voltage pulses.

a, Zoom-in view of the programing characteristics showing the readout of four discrete conductance states with low read noise during the 10 microseconds sensing period shaded in green, after 10 microseconds settling time, out of the 300 conductance states shown in Fig. 2b. Red dotted lines serve as visual guide to mark the average channel conductance in each state. b, Zoom-in view of the read-out conductance (black circle) after the corresponding weight-update pulses. The red solid line is the expected conductance value obtained through fitting the depression curve. The small deviation of the experimental data to the expectation indicates small cycle-to-cycle variation. Blue dotted lines serve as visual guide to mark the measured conductance values on y axis.

Extended Data Fig. 4 ECRAM pulse-measurement setups to extract the read transients.

a, Measurement configuration to extract tread. WGFMUs are connected to the ECRAM source and drain terminals. The gate is grounded. During measurement, the voltage pulse is applied on the drain side and the other channel of WGFMU reads the current signal. b, Measurement configuration to perform the microsecond pulse write operations and extract tread-after-write. WGFMUs are connected to the ECRAM gate and drain terminals. The source is grounded. During measurement, the voltage pulse is applied on the gate terminal for the weight-update and the other channel of WGFMU applies a small voltage pulse to reads the current flowing across the channel afterwards. SMU: source-measurement unit (Keysight B1517A). WGFMU: waveform generator/fast-measurement unit (Keysight B1530A). GND: ground. Red and blue dashed lines mark the WGFMU and SMU channels, respectively.

Extended Data Fig. 5 Platinum contact resistance to HxWO3.

a, SEM micrograph showing the transmission-line structure fabricated with Lch varied from 6 µm down to 150 nm but identical W of 60 µm. Scale bar, 50 µm. b, Width normalized overall resistance R as a function of Lch for HxWO3 switched between high (180 MΩ·sq-1) and low (150 kΩ·sq-1) sheet resistance corresponding to the operating dynamic range of ECRAM, showing a degradation of the device on/off ratio with the scaling of the Lch.

Extended Data Fig. 6 HxWO3 channel after the endurance test.

a, STEM micrograph showing the gate stack of the ECRAM after operation with 100 million read-write cycles. Scale bar, 100 nm. b, The depth profiles showing the atomic fractions of W (black), Hf (blue), and O (red) before (solid lines) and after (dotted lines) the 108 cycle endurance test, as measured by energy dispersive X-ray spectroscopy. The orange dashed line serves as a visual guide to mark the interface between WO3 and HfO2.

Extended Data Fig. 7 Operation and reliability of all-inorganic protonic ECRAMs under elevated temperature.

a, Programing of an all-inorganic protonic ECRAM with Al2O3 passivation measured at the same temperature after being annealed at 100 °C (black square), 150 °C (red circle), and 200 °C (blue triangle), respectively. b, Programing an all-inorganic protonic ECRAM at 80 °C (black) and 100 °C (red). G0 and ∆G increased due to the thermal excitation of additional carriers in the HxWO3 channel and the increase of proton diffusivity, respectively. c, Logarithmic scale plot showing the average ∆G per weight-update step as a function of the device operating temperature. Red dotted line represents the linear fitting to the data. d, Retention of the fully on-state conductance of the ECRAM cell at 80 °C (black) and 100 °C (red), and the corresponding drift coefficient (v), measured with the gate floating. e, ECRAM endurance test at 80 °C for 107 write-read pulses, showing no device degradation with the intermediate switching cycles plotted after 104, 105, 106, and 107 pulses.

Extended Data Fig. 8 One-transistor-one-ECRAM cell fabrication flow.

Schematics illustrating the process flow to fabricate a 1-transistor-1-ECRAM memory cell, consisted of an all-inorganic protonic ECRAM and a silicon MOSFET in different layers monolithically integrated together on a SOI wafer substrate.

Extended Data Fig. 9 Current-voltage characteristics of the silicon MOSFET selector measured before (part a) and after (part b) fabricating the protonic ECRAM layer on top with 40 nm HfO2 as the interlayer dielectric.

VDS: source-drain bias; IDS: source-drain current.

Extended Data Fig. 10 Device-to-device variation extracted from 8×8 ECRAM array.

a, Optical micrograph showing the completed 8 by 8 ECRAM array. Scale bar, 500 µm. b-d, Spatial mapping of the non-linearity (part b, standard deviation around 10%), minimum conductance (part c, standard deviation about 12%), and maximum conductance (part d, standard deviation about 13%) of the fabricated ECRAMs. Red indicated failed devices resulting from lithography or material defects. e-f, Collections of the programing characteristics of ECRAMs in row 1-4 (from top to bottom, part e) and row 5-8 (part f) of the array, respectively.

Supplementary information

Supplementary information

Supplementary Notes 1–7, Figs. 1–7, Tables 1 and 2 and refs. 1–42.

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Cui, J., An, F., Qian, J. et al. CMOS-compatible electrochemical synaptic transistor arrays for deep learning accelerators. Nat Electron 6, 292–300 (2023). https://doi.org/10.1038/s41928-023-00939-7

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