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A memristive deep belief neural network based on silicon synapses


Memristor-based neuromorphic computing could overcome the limitations of traditional von Neumann computing architectures—in which data are shuffled between separate memory and processing units—and improve the performance of deep neural networks. However, this will require accurate synaptic-like device performance, and memristors typically suffer from poor yield and a limited number of reliable conductance states. Here we report floating-gate memristive synaptic devices that are fabricated in a commercial complementary metal–oxide–semiconductor process. These silicon synapses offer analogue tunability, high endurance, long retention time, predictable cycling degradation, moderate device-to-device variation and high yield. They also provide two orders of magnitude higher energy efficiency for multiply–accumulate operations than graphics processing units. We use two 12 × 8 arrays of memristive devices for the in situ training of a 19 × 8 memristive restricted Boltzmann machine for pattern recognition via a gradient descent algorithm based on contrastive divergence. We then create a memristive deep belief neural network consisting of three memristive restricted Boltzmann machines. We test this system using the modified National Institute of Standards and Technology dataset, demonstrating a recognition accuracy of up to 97.05%.

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Fig. 1: Memristive synapses based on two-terminal floating-gate devices.
Fig. 2: Memristive synaptic array and device-to-device variations.
Fig. 3: Setup of the test system for array operations and memristive RBM demonstration.
Fig. 4: Demonstration of RBM training using two memristive synaptic chips.
Fig. 5: Training of a DBN based on silicon synapses for the MNIST dataset.

Data availability

The data that support the plots within this paper and other findings of this study are available as Source data.

Code availability

The code that supports the device modelling and neural network simulations in this study is provided as Supplementary Source Code and is also available via GitHub at


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This work was supported by the European Research Council through the European Union’s Horizon 2020 Research and Innovation Programme under grant 757259 and FET-Open NeuChip project under grant agreement no. 964877. W.W. was supported in part at Technion by the Aly Kaufman Fellowship. W.W. acknowledges help from D. Dutta on the PCB and FPGA code development.

Author information

Authors and Affiliations



W.W. conceived the concept of Y-Flash memristor-based RBM and DBN. L.D. designed the memristive chip and led the tapeout to fabrication, including array layout and readout cells, and developed the device-level operation schemes. Y.R and E.P. suggested the Y-Flash memristor cell and performed the initial verification. W.W. conducted the device characterization, array-level operation schemes with the assistance of L.D., E.H. and B.H. W.W. conducted the neural network demonstration and simulations with the assistance of L.D. and Y.L. Y.R., E.P. and Z.W. helped with the illustration results. All the authors discussed the results and contributed to the preparation of the manuscript. S.K. supervised the research.

Corresponding authors

Correspondence to Wei Wang or Shahar Kvatinsky.

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Nature Electronics thanks the anonymous reviewers for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Device structure and band diagrams in different operational modes.

Schematic illustration of the device structure from the sectional view. The injection transistor (shorter channel and higher threshold voltage) and the read transistor (longer channel and lower threshold voltage) are parallelly connected: they have a common drain and a common floating gate; their sources are externally shortened. The capacitance between the floating gate and the drain (\(C_{GD}\) is much larger than other capacitances), thus the floating gate voltage is mainly coupled to the drain. (b) The equivalent circuit symbol of the device. (c) Band diagrams of the read transistor in the reading mode. A low drain voltage will induce a low floating gate voltage and keep the transistor closed. As the drain voltage increases, the floating gate voltage increases, and the transistor gradually opens. The injection transistor shares similar behaviour but has a lower current since the threshold voltage is higher. (d) The band diagram of the injection transistor at the depression (program) mode. When a higher voltage is applied to the drain and the source is grounded, the electrons in the channel are accelerated by the electrical field in the drain region, and the lucky ones are injected into the floating gate, that is, channel hot electron injection (CHEI). (e) The band diagram of the injection transistor in the potentiation (erase) mode. When a higher voltage is applied to the source and the drain is grounded or floating, the source p-n junction is reversely biased. This induces band-to-band (B2B) hole generation in the source region. The high lateral electric field accelerates the generated holes, and the lucky ones are injected into the floating gate. The hot electron/hole effects are negligible in the readout transistor.

Extended Data Fig. 2 Depression and potentiation of the devices by continuous program or erase pulses.

(a) Read mode of the device by applying a voltage pulse (VR = 2 V for pulse reading) on the D terminal and sensing the current (IR). (b) Depression (program) mode of the device operation by applying a voltage pulse (VP = 5 V) on the D terminal and grounding the S terminal. (c) Potentiation (erase) mode of the device operation by applying a voltage pulse (VE = 8 V) on the S terminal and grounding, or floating, the D terminal. The floating D terminal will be capacitively coupled to the grounded substrate. (d) Schematic of the pulse depression/program test by alternatively applying the program pulse and reading the device by the read pulse. (e) The device conductance (G = IR/VR) as a function of the pulse number when depressing the device by programming pulses with the width of 10 us. (f) Schematic of the pulse potentiation/erase test by alternatively applying the erase pulse and reading the device by the read pulse. (g) The device conductance as a function of the pulse number when potentiating the device by erasing pulses with the width of 10 us.

Source data

Extended Data Fig. 3 Depression, potentiation, and continuous readout operations of the devices.

(a) Depression (program) of the device by 200 μs pulses. (b) Potentiation (erase) of the device by 100 μs pulses. (c) The conductance of the device as a function of time after each program pulse by continuously reading the state of the device for 20 seconds. (d) The conductance of the device as a function of time after each erase pulse by continuously reading the state of the device for 20 seconds.

Source data

Extended Data Fig. 4 Cycling degradation and its modeling.

(a) Continuously depression/program of one device from the high conductance state (HCS) to the low conductance state (LCS) for 400 test cycles. (b) Continuously potentiation/erase of one device from the LCS to the HCS for 400 test cycles. (c) The program time (pulse number multiplied by the pulse width) needed for programming the device from HCS to LCS as a function of the cycling number. Both the experimental data and simulation results are presented in the figure. (d) The erase time needed for erasing the device from LCS to HCS as a function of the cycling number.

Source data

Extended Data Fig. 5 Setup of the testing system.

The schematic setup of the test system for array operations and memristive RBM demonstration.

Extended Data Fig. 6 Modelling of device-to-device variations.

(a) Simulated device-to-device variations of the depression/program behavior (red line: a typical depression curve; gray lines: all depression curves of other devices). (b) Simulated device-to-device variations of the potentiation/erase behavior. (c) Statistical result of total program times in different devices compared with simulation results. (d) Statistical result of total erase times in different devices compared with simulation results.

Source data

Extended Data Fig. 7 Flow chart of the online training of RBM including test algorithm after each training epoch.

The VMM and weight updates are performed in the memristive array using the testing system. The stochastic sampling, as well as the calculation and accumulation of the contrastive divergence (CD), are performed in software.

Extended Data Fig. 8 Full hardware design of the memristive part of an RBM layer.

The memristive part of an RBM layer conducts the forward and backward VMMs as well as the stochastic sampling in the analog domain. The peripheral circuit includes multiplexers, trans-impedance amplifiers, noise current generators, and comparators. No digital-to-analog converters (DACs) or analog-to-digital converters (ADCs) are needed in the peripheral circuit. Other parts of the memristive RBM and DBN are all digital circuits.

Supplementary information

Supplementary Software

Source code for device modelling of the two-terminal floating-gate memristor model and the online training of memristive DBN.

Source data

Source Data Fig. 1

Source data for Fig. 1c–e.

Source Data Fig. 2

Source data for Fig. 2d–g.

Source Data Fig. 4

Source data for Fig. 4f–j.

Source Data Fig. 5

Source data for Fig. 5b–d.

Source Data Extended Data Fig. 2

Source data for Extended Data Fig. 2e,g.

Source Data Extended Data Fig. 3

Source data for Extended Data Fig. 3a–d.

Source Data Extended Data Fig. 4

Source data for Extended Data Fig. 4a–d.

Source Data Extended Data Fig. 6

Source data for Extended Data Fig. 6c,d.

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Wang, W., Danial, L., Li, Y. et al. A memristive deep belief neural network based on silicon synapses. Nat Electron 5, 870–880 (2022).

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