Multimode transistors and neural networks based on ion-dynamic capacitance

Abstract

Electrolyte-gated transistors can function as switching elements, artificial synapses and memristive systems, and could be used to create compact and powerful neuromorphic computing networks. However, insight into the underlying physics of such devices, including complex ion dynamics and the resulting capacitances, remains limited. Here we report a concise model for the transient ion-dynamic capacitance in electrolyte-gated transistors. The theory predicts that plasticity, high apparent mobility, sharp subthreshold swing and memristive conductance can be achieved—on demand—in a single transistor by appropriately programming the interfacial ion concentrations or matching the scan speed with ion motions. We then fabricate such multimode transistors using common solid-state electrolyte films and experimentally confirm the different capabilities. We also show in software that the multimode devices could be used to create neural networks that can be switched between conventional artificial neural networks, recurrent neural networks and spiking neural networks.

Main

Electrolyte-gated transistors offer low operational voltages and high output currents, as well as a range of other attractive features^1,2,3,4. A variety of artificial synapses and memristive systems have, for instance, been developed using such devices and by exploiting the spatiotemporal dependency of ionic motion^{5,6,7,8,9,10,11}. As ions in dielectrics are driven by gate biases to approach or move away from the semiconductor/dielectric interface, the transistors exhibit transient currents that can emulate various synapse-like behaviours including paired-pulse facilitation, short-term memory and long-term memory^12,13,14. The accumulation of ions can also induce large capacitances due to electric double layers and pseudocapacitance^15,16. By using these effects, combined with devices based on two-dimensional materials, the turn-on properties of transistors have been pushed to below the thermionic limit^17,18,19,20, that is, a reversed subthreshold slope below 60 mV dec^–1 at room temperature. With such features, electrolyte-gated transistors offer new approaches to create dense, low-power integrated circuits; sensitive biosensors and gas sensors; and compact and powerful neuromorphic computing networks^{21,22,23,24,25}.

Despite this progress, insight into the underlying physics of devices and their various capabilities remains limited. In contrast to a static system, the ion-dynamic capacitance of the electrolyte is not a constant but a function of bias and time. The electrostatic potential also does not drop linearly within the dielectric but mainly drops at the electrolyte/semiconductor interface²⁶, which increase the complexity of the spatiotemporal evolution of ion concentrations, electrostatic potential, effective capacitance and charge accumulation in the channel.

In this Article, we report a compact theory for time- and gate-dependent current in transistors with solid-state electrolytes. The theory predicts that the features of plasticity, high apparent mobility, sharp subthreshold swing and memristive conductance could appear on demand in a single transistor by programming the ion distribution or sweeping speeds. We validate this with numerical simulations. We then fabricate such multimode transistors using thin films (10 nm thick) of semiconducting indium oxide (InO_x) and thin films (40 nm thick) of the solid-state electrolyte aluminium oxide (AlO_x) or zirconium oxide (ZrO_x). We also show, in software, that multimode devices could be harnessed to create neural networks that function in different modes as needed.

Physics of ion-dynamic capacitance

The device structure, density of ions p(x, t) (cation, cm⁻³) and electrostatic potential V(x, t) are illustrated in Fig. 1a,b. The p and V values under constant bias change from the initial to the transient and steady states (Fig. 1b). In quantity, p and V are spatiotemporally coupled in the drift–diffusion equation based on the drift flux density S_drift and diffusion flux density S_diffusion:

$$\begin{array}{l}\frac{{\partial p\left( {x,t} \right)}}{{\partial t}} = - \nabla S_{{{{\mathrm{diffusion}}}}} - \nabla S_{{{{\mathrm{drift}}}}} = \left[ {D_{{{\mathrm{i}}}}\frac{{\partial ^2p\left( {x,t} \right)}}{{\partial x^2}}} \right]\\ - \left[ {\mu _{{{{\mathrm{ion}}}}} E\left( {x,t} \right)\frac{{\partial p\left( {x,t} \right)}}{{\partial x}} + \mu _{{{{\mathrm{ion}}}}} p\left( {x,t} \right)\frac{{\partial E\left( {x,t} \right)}}{{\partial x}}} \right],\end{array}$$

(1)

where D_i is the diffusion coefficient, E(x, t) = –∂V(x, t)/∂x is the electric field and µ_ion = (D_ie)/(k_BT) is the ionic mobility (with elementary charge e, Boltzmann constant k_B and temperature T). The analytical solution of equation (1) and Poisson equation for the unconstrained or steady situation are provided in Supplementary Note 1. For simplicity, we mainly consider the time-dependent ion density at the semiconductor/dielectric interface as p(0, t) = p_i, the dimensionless potential drop u (Fig. 1b), induced capacitance C and total charges Q_i. To consider the large potential drop near the interface, the dimensionless potential u is used for the following discussions. We refer to the typical dispersive process (with energy distribution)²⁷ and the electric double layer theory²⁸, and develop a set of approximated solutions for them (Supplementary Note 2).

$$\frac{{\partial p_{{{\mathrm{i}}}}}}{{\partial t}} = - \left( {p_{{{\mathrm{i}}}} - p_{{{{\mathrm{i}}}}\infty }} \right)\frac{\beta }{\tau }\left( {\frac{t}{\tau }} \right)^{\beta - 1}$$

(2)

$$u = {{{\mathrm{ln}}}}\left( {\frac{{\gamma _1 - 1 - \sqrt {1 + 2\gamma _1\gamma _2 - 2\gamma _1} }}{{\gamma _1 - 2\gamma _2}}} \right)$$

(3)

$$C = C_0\frac{{{{{\mathrm{cosh}}}}\left( {\frac{u}{2}} \right)}}{{1 + 2\gamma _1{{{\mathrm{sinh}}}}^2\left( {\frac{u}{2}} \right)}} \sqrt {\frac{{2\gamma _1{{{\mathrm{sinh}}}}^2\left( {\frac{u}{2}} \right)}}{{{{{\mathrm{ln}}}}\left[ {1 + 2\gamma _1{{{\mathrm{sinh}}}}^2\left( {\frac{u}{2}} \right)} \right]}}}$$

(4)

$$Q_{{{\mathrm{i}}}} = \left( {p_{{{\mathrm{i}}}} - n_{{{\mathrm{i}}}}} \right)et_{{{\mathrm{E}}}}$$

(5)

Fig. 1: Theory of ion-dynamic capacitance in transistors.

a, Schematic of electrolyte-gated transistors. Q_i and Q_s represent the ions and charge carriers on either side of the dielectric/semiconductor interface, respectively. V(x) and x represent the electrostatic potential within the dielectric and distance from the interface, respectively. S, source; D, drain. b, Schematic of the dynamic motion of cations (blue dots) and anions (red dots) under constant bias with the profile of V(x) (dashed line). V_ox is the voltage drop from the gate to the dielectric/semiconductor interface; S_drift and S_diffusion are the drift and diffusion flux density, respectively; D_i,n and D_i,p are the diffusion coefficients; and u is the dimensionless potential. The density of ions transferred from electrolyte into semiconductor is λ₁p_i. c,d, Under constant bias V_g, the calculated p_i, u and C/C₀ at V_ox = 0.1 V (c) or V_ox = 50 V (d). The t₀ value is the transit time defined as $t_{{{{\mathrm{0}}}}} = d_{{{{\mathrm{ox}}}}}^2/\left( {\mu _{{{{\mathrm{ion}}}}}V_{{{{\mathrm{ox}}}}}} \right)$, where d_ox is the thickness of the electrolyte. e,g, Under triangular waves V_g, the interfacial ion concentration with various sweep rates s (e), capacitance ratio C/C₀ as a function of dimensionless potential u (f) and capacitance ratio C/C₀ as a function of V_g (g). In f, the dashed line is the whole C/C₀–u curve to show the tendency.

Source data

In equation (2), the time constant τ, power factor β and p_i∞ are described by τ = η/(|V_ox|D_i), β = β₀|V_ox/1|^α and p_i∞ = p_i,max[1 – Aexp(–V_ox/V₀)], respectively, where η, β₀, α, p_i,max, A and V₀ are constants, because the process is driven by voltage V_ox and the rate is limited by diffusion coefficient D_i. In equations (3) and (4), γ₁ is the initial-to-steady density ratio γ₁ = (p_i0 + n_i0)/p_i,max, γ₂ is the initial-to-transient density ratio γ₂ = p_i0/p_i and C₀ is the Debye capacitance $C_0 = \sqrt {\varepsilon _0\varepsilon _{{{\mathrm{r}}}}e^2\left( {p_{{{{\mathrm{i}}}}0} + n_{{{{\mathrm{i}}}}0}} \right)/\left( {4\uppi k_{{{\mathrm{B}}}}T} \right)}$. When applied with constant bias, equation (2) turns into an integral form (Supplementary Note 2 and Supplementary Fig. 4). The possible ion transfer from electrolytes into semiconductors is considered by a transferred ratio λ₁ (0 ≤ λ₁ < 1).

The p_i, u and C values with various V_ox or D_i values are calculated by equations (2)–(4) in the case without interfacial ion transfer (λ₁ = 0) and is verified by the numerical simulation (Supplementary Fig. 2). With a constant low V_ox or a high V_ox (Fig. 1c,d), u and C increase with time as p_i accumulates (white areas) and then saturate or drop once p_i saturates (red areas). With a triangle wave of gate bias, the interfacial ions are driven to accumulate or release with the anticlockwise hysteresis (Fig. 1e), with u and C changing accordingly (Supplementary Fig. 3). As p_i increases, C increases until the maximum where u is denoted as u_M (Fig. 1f). If p_i continues to increase, the piled-up ions would spread into the bulk due to their volumes (steric effect) and the effective capacitor thickness $L_{{{{\mathrm{eff}}}}} \propto L_{{{\mathrm{D}}}}\sqrt {2\gamma _1u}$ is increased with decreased C (Fig. 1f, bottom; blue arrow), where L_D is the Debye length²⁸. Alternatively, if p_i decreases, the dielectric film acts toward a parallel-plate capacitor (Fig. 1f, bottom; red arrow). In either case, the effective capacitor thickness increases and C decreases, giving the gull-wing-shaped C–u relation (Fig. 1f, dashed curves). If decreasing the sweep rate s or increasing diffusion coefficient D_i, the C–u curves would cover wider ranges as indicated by the increased Δu (Fig. 1f, from top to bottom). The evolution leads to complex C–V_g relations (Fig. 1g) that are crucial to achieve multimode transistors.

The compact model equations (2)–(5) could be combined with the field-effect transistor (FET) equations to give current–voltage (I–V) relations (Supplementary Fig. 4), where the charges of ions Q_i also cause shift in the flat-band voltage V_FB against its initial value V_FB0, that is, V_FB = V_FB0 − Q_i/C. The theory can be extended by using the non-zero transferred ratio λ₁ to describe that some ions transferred from the solid-state electrolytes into semiconductors (for example, Faraday charge transfer) dope semiconductors and affect the conductivity²⁹. It can also be extended by using the condition D_i,n ≫ D_i,p (or D_i,n ≪ D_i,p) to cover the case that only one type of ion is mobile (Supplementary Note 4). The theory predicts that multimode operation could be obtained in a single transistor with an ionic dielectric and will be presented together with experiments later.

Ions in solid-state electrolytes

To achieve multimode transistors, we fabricated a commonly used metal-oxide dielectric, AlO_x, by a sol–gel process followed by annealing at a low or high temperature (300 or 500 °C, respectively). The AlO_x film forms an abrupt interface with the highly crystalline indium oxide semiconductor to allow transistor fabrication, as revealed by transmission electron microscopy (TEM) with energy-dispersive spectrometry mapping (Fig. 2a). To identify the ions, the X-ray photoelectron spectroscopy was measured (Fig. 2b), where both O1s peak and Al2p peak of the 300 °C-annealed AlO_x film (‘low T’) shift positively compared with those of the 500 °C-annealed film (‘high T’). By referencing the peak positions of aluminium compounds, the shift in O1s and Al2p peaks towards higher energies in low-T AlO_x is possibly due to the formation of Al(OH)₃ or AlOOH after dehydration condensation³⁰. Hydrogen ions possibly act as the movable ions to give the electrolytic properties. The ²⁷Al nuclear magnetic resonance (NMR) was measured to examine the Al environment (Fig. 2c), where three resonances corresponding to the tetrahedral (~72 ppm), pentahedral (~38 ppm) and octahedral (~9 ppm) Al coordination are found. In low-T AlO_x, Al(O)₆ decreases from 88% to 79%, whereas Al(O)₄ increases from 9% to 15%. Because Al(O)₄ has greater acidity than Al(O)₆ and it causes ionic polarization³¹, the conversion of Al(O)₆ to Al(O)₄ indicates an increase in H⁺ concentration. The 3.7 ppm left shift of the Al(O)₄ peak in low-T AlO_x possibly contributes to stronger magnetic shielding induced by the high H⁺ concentration³².

Fig. 2: Ions and capacitances of solid-state electrolyte AlO_x.

a, High-resolution transmission electron microscopy image of the indium oxide layer (top left) and the corresponding fast Fourier transform image (bottom left). The spots encircled by the red circle correspond to the (400) plane of indium oxide nanocrystals. The TEM cross-section image of Si/AlO_x/InO_x and the corresponding energy-dispersive spectrometry mapping (middle). Schematic of AlO_x/InO_x with residual hydrogen (right). b, X-ray photoelectron spectroscopy measurement of the O1s and Al2p peak of AlO_x annealed at 300 °C (low T) and 500 °C (high T) (left). Comparison of the O1s and Al2p peak positions (right). c, ²⁷Al NMR of AlO_x. d, Experimentally measured capacitance as a function of electrode potential V, from 1 Hz to 10 kHz. e, Experimentally measured capacitance as a function of converted u. f,g, Bode impedance plot (f) and Bode angle plot (g) of a low-temperature solution-processed AlO_x capacitor at various bias voltages.

Source data

The low-T AlO_x film exhibits the frequency- and voltage-dependent capacitance following the theoretically predicted u–C relations (Fig. 2d,e), implying it meets the required ionic electrolyte properties predicted in our model. The electrochemical impedance spectroscopy data at various bias voltages (Fig. 2f,g) follow the Randles cell including electric double layer capacitances^33,34,35, in contrast with that of thermally grown SiO₂ following a standard resistor–capacitor cell (Supplementary Fig. 5). The electrochemical impedance spectroscopy and cyclic voltammograms are comprehensively analysed with models in Supplementary Note 3 and the estimated parameters of ions are as close to those in the literature (Supplementary Figs. 6–8)^36,37.

Multimode transistors

The theory (equations (2)–(5)) predicts multimode operation could be obtained by presetting the ion concentration p_i (for example, with V_g programming), varying the diffusion rate D_i or changing the sweep rate s = ∂V_g/∂t (Fig. 3a–d) and validated by numerical simulation (Fig. 3e–h). On potentiation with different amplitudes or widths of pulses, the transistor shows short-time plasticity (STP) or long-time plasticity (LTP) (Fig. 3a,e), or an enhanced current and apparent mobility after a high gate bias, that is, the ultrahigh-apparent-mobility mode (Fig. 3b,f). By further increasing s (or sweep range of V_g), the hysteresis curve shows an ultrasharp reversed subthreshold slope SS of about 30 mV dec^–1 in both forward and backward curves, that is, the subthermionic SS mode (Fig. 3c,g); or even the hysteresis with negative transconductance, that is, the memristive mode (Fig. 3d,h). In experiments, we used a very thin semiconductor InO_x film (10 nm) and the above solid-state electrolyte AlO_x film (40 nm) or ZrO_x and to fabricate bottom-gate, top-contact FETs. The maximum of leakage current is lower than 7% of I_d. As shown in Fig. 3i–l, all the abovementioned modes could be obtained by presetting V_g or changing s. The above multimode characteristics maintain at least ten months after storage, indicating good long-term stability. The features have been repeated in more than 20 devices in different batches (Supplementary Note 5). The consistent simulation and experimental results validate the theoretical predictions and applicability of strategy.

Fig. 3: Multimode transistors in the theory, simulations and experiments.

a–d, Calculated I–V characteristics (V_d = 0.1 V) from the above model by varying the sweep rate s (s = 2.40 V s^–1 (b); s = 1.20 V s^–1 (c); s = 0.24 V s^–1 (d)). I_d–t curves under the stimulation of pulses and relative change in conductance ΔG% (a). After the stimuli (Supplementary Note 6), the EPSC is observed. b, Transfer characteristics and extracted apparent mobility μ. c, Transfer characteristics and reversed subthreshold slope SS for forward or backward curves. d, Transfer characteristics and transconductance g_m. e–h, Numerical simulations by solving equation (1) and Poisson equation (V_d = 0.1 V) with varying s (s = 2.5 V s^–1 (f); s = 1.0 V s^–1 (g); s = 0.1 V s^–1 (h)). i–l, Experimental results of the InO_x/AlO_x transistor with the corresponding modes in a–d (i–l), respectively (some were obtained after programming the device).

Source data

The complex transistor modes—tunable plasticity mode, ultrahigh-apparent-mobility mode, subthermionic SS mode and memristive mode—are summarized in Fig. 4a, and the evolution of electrostatic potential and charges are illustrated in Fig. 4b–d.

Fig. 4: Mechanisms and parameters of multimode transistors.

a, Summary of multiple modes within the p_i–t coordinates, where Δu and u_M are illustrated in Fig. 1f. b, Schemes of the potential near the semiconductor/dielectric interface for different modes. c, Corresponding diagrams of Q_i–V or Q_i–t curves. d, Corresponding diagrams of I–V or I–t curves. e, Extracted apparent mobility μ and reversed subthreshold slope SS (circle, forward scanning; triangle, backward scanning) dependent on the key parameter θ, with fitting by equations (6) and (7). f,g, Extracted μ in the InO_x/AlO_x transistor obtained by varying the sweep rate s (f) or varying the programming wave of V_g applied before transfer scanning (g). h,i, Extracted SS under various s values (h) or varying the wave of V_g (i). The minimum SS values were extracted in the negative V_g region and the absolute value |V_g| is used here. The error bars denote the data extracted from four measurements and presented as mean values ± standard deviation.

Source data

Tunable plasticity mode: this occurs when ions are gradually accumulated and Δu gently increases with Δu ≪ u_M (Fig. 4a, purple segment). As C gently increases (Fig. 1g, top), the electrostatic potential V(x) and interfacial ions p_i gently increase (Fig. 4b–d, mode I). The number of ions participating in the operation can be easily controlled by adjusting the amplitude and number of V_g pulses. With a small (large) preset p_i or large (small) D_i, potentiation is short (long), enabling STP (LTP) in the synaptic behaviour.

Ultrahigh-apparent-mobility mode: when ions synchronously increase with the V_g sweep, Δu substantially increases towards u_M (Fig. 4a, orange segment), C sharply increases (Fig. 1g, middle), and substantial carriers are induced with a large potential drop near the interface (Fig. 4b–d, mode II; simulation in Supplementary Fig. 18). As C in equation (3) is comparable with the Debye capacitance C₀, it can substantially exceed the geometric capacitance C_ox = ε₀ε_r/d_ox for extracting apparent mobility µ = g_mL/(WC_oxV_d), where g_m = ∂I_d/∂V_g. For example, C₀ is 9.0 μF cm^–2 if p_i0 = 10²⁰ cm⁻³ and would approach C_ox = 0.2 μF cm^–2 only if p_i0 < 10¹⁷ cm⁻³ (Supplementary Fig. 19). For simplification, in the case that p_i is much less than the maximum values, the ratio between the apparent mobility μ and real μ₀ is approximated as

$$\frac{\mu }{{\mu _0}} = \frac{1}{{C_{{{{\mathrm{ox}}}}}}}\frac{{\partial Q_s}}{{\partial V_{{{\mathrm{g}}}}}} \approx \frac{\theta }{{C_{{{{\mathrm{ox}}}}}}} \frac{V_{{{\mathrm{g}}}}{\beta _0t_\mathrm{E}^2}}{\eta } \propto \frac{{D_{{{\mathrm{i}}}}p_{{{{\mathrm{i}}}}0}}}{s},$$

(6)

where the characteristic capacitance is θ = e(2/γ₁ – 1/γ₂)p_i0D_i/(st_E) ∝ D_ip_i0/s (Supplementary Note 7) and t_E is the thickness of the electric double layer. Apparent μ will increase with reducing s, increasing p_i or enlarging D_i. The simulation results (Fig. 4e and Supplementary Figs. 20 and 21) effectively follow equation (6) as well as the experimental results obtained from reducing s (Fig. 4f and Supplementary Fig. 22), presetting p_i (Fig. 4g and Supplementary Fig. 23), or varying the ion concentration in dielectrics³¹. This also means that the real carrier mobility in transistors with ionic dielectrics could not be determined by only measuring the quasi-static capacitances³⁸. The high-apparent-mobility mode increases the current density but the current decay gradually due to the thermally activated ion diffusion (Supplementary Fig. 25)^39,40. As the decay time (≫500 s) is much longer than the subsecond V_g pulse for programming (Supplementary Fig. 23), this mode can be maintained without the need to frequently refresh.

Subthermionic SS mode: when ions are synchronously released with V_g sweep, u increases and then decreases (Fig. 4a, green segment). As the ions accumulated at the interface are released to the bulk with decreased p_i and potential V (Fig. 4b–d, mode III), the current sharply changes; if the rate of ion release matches the rate of V_g sweep, a negative ∂V_ox/∂V_g would appear with SS < (kT/e)ln10 (Supplementary Fig. 29). A higher matching degree, characterized by the response of ion-induced potential u to V_g (that is, ∂u/∂V_g), leads to more ions released to the bulk and a smaller SS (Supplementary Figs. 30 and 31). Note that the subthermionic SS can be obtained during the forward curve, backward curve or both curves, if the ions are synchronously released with V_g scanning (Supplementary Note 4 and Supplementary Fig. 12). This theory is confirmed by simulations and experiments (Fig. 3g,k and Supplementary Figs. 32–36). The SS is approximated as

$$\mathrm{SS} = \frac{{\partial V_{{{\mathrm{g}}}}}}{{\partial {{{\mathrm{log}}}}_{10}I_{{{\mathrm{d}}}}}} = \frac{{kT}}{e}{{{\mathrm{ln}}}}10/\left( {1 - \frac{{\partial V_{{{{\mathrm{ox}}}}}}}{{\partial V_{{{\mathrm{g}}}}}}} \right) \approx \frac{1}{{1 + \left( {a\theta - b} \right)/C_0}}\frac{{kT}}{e}{{{\mathrm{ln}}}}10,$$

(7)

where V_ox = V_g − φ_s and a and b are constants (Supplementary Note 8). The simulation results follow equation (7) well (Fig. 4e). The experimental results further verify that smaller SS could be obtained by programming more interfacial ions to match the gate-field switching by varying the range of V_g scanning or sweep rate s (Fig. 4h,i and Supplementary Figs. 34–36). Combining equations (6) and (7), the characteristic capacitance θ ∝ D_ip_i0/s could be taken as the key parameter to govern the transition from conventional to unconventional transistor characteristics, featuring very high apparent μ and ultrasharp SS.

Memristive mode: when ions are post-saturated, Δu could exceed u_M (Fig. 4a, pink segment). As C reaches the maximum and then decreases due to the steric effects of ions (Fig. 1g, bottom, and Supplementary Fig. 37), the potential V near the interface decreases, resulting in a decrease in I_d (Fig. 4d–f, mode IV). The detailed mechanisms are explained with the evolution of ion concentration and electric field (Supplementary Note 9). This mode disappears if ions substantially transfer from the electrolyte into the semiconductor and the steric effect disappears (Supplementary Note 4). The observation of such a mode in experiments implies that ion transfer may not be notable. During the forward sweep in the experiment, the FET changes from the low-resistance state to the high-resistance state at V_g ≈ 6 V (Fig. 3i). The feature with negative g_m can be intensified if θ ∝ D_ip_i0/s increases (Supplementary Fig. 39). The resistance reverses when the state variable p_i is close to the maximum, resembling that in memristors⁴¹. Specifically, the I_d = g_m(p_i, V_g, t) × (V_g – V_th) relationship follows that of the extended memristor⁴², because g_m is the function of p_i with ∂p_i/∂t = f(p_i, V_g, t). During the backward sweep, I_d intersects with the forward curve, also similar to the pinched hysteresis loop as the key feature of memristors claimed elsewhere⁴². To obtain such a mode, the initial-to-steady density ratio γ₁ should be small to allow u to reach u_M within the measurement (Supplementary Fig. 38).

The above modes could be coupled to generate second-order features. Mode I with plasticity and mode II with high apparent μ could coexist and enable a visualized synapse in the form of thin-film transistor (TFT)–light-emitting diode (LED) integration, where luminance could be held after gate-off by the excitatory postsynaptic current (EPSC)—a potentiated current triggered by a potential spike signal in a presynaptic neuron^43,44 (Supplementary Fig. 42 and Supplementary Videos 1 and 2). Mode I and mode III could be combined to generate the leaky-integrate-and-fire (LIF) behaviour emulating biological neurons^45,46. Consecutive pulses shift V_th and simultaneously change g_m, inducing the subthreshold to above-threshold transition and abrupt increase in I_d. A shorter time of stimuli to trigger the firing process can be obtained by changing several device parameters (Supplementary Fig. 44). In both theoretical calculation and experimental measurements, the LIF behaviour is obtained (Supplementary Fig. 43). In general, to reproduce all these modes, the change in ion concentrations for both ion species should be large enough to give a prominent dynamic capacitance with the interfaces suitable for accumulating ions. In this study, the low-temperature processed AlO_x limits the choice of semiconductors to some extent. By far, we have observed all the four operation modes only in transistors with solution-processed or vacuum-deposited indium oxide (Supplementary Fig. 41). Nevertheless, the presented devices enable multimode operations by using the non-crystalline electrolytes with simple fabrication.

Multimode neural networks

The multimode transistors can enable multimode neural networks: STP for artificial neural networks (ANNs), LTP for recurrent neural networks (RNNs) and LIF behaviour for spiking neural networks (SNNs).

ANN

With short gate pulses (2 V; duration, 20 ms; period, 40 ms), the increased conductance G = I/V recovers soon (STP; Fig. 5a) and could serve as the weight of the neuron. The experimental results are used to generate the cumulative probability distribution function (CDF) of G and its error ΔG (Fig. 5b), forming the weight update rule under potentiation or depression pulses. The device conductance in STP (the same below for LTP and LIF) were measured and written into the software for training the neural networks, which perform the image recognition tasks. A backpropagation ANN was built to classify the handwritten digits (Fig. 5c)^47,48,49,50, giving an accuracy of 85% for large digits (28 × 28 pixels) and 93% for small digits (8 × 8 pixels) after 40 epochs (Fig. 5d).

Fig. 5: Multimode neural networks.

a, Experimental STP characteristics of a transistor. b, CDF of conductance G and error ΔG. c, Scheme of ANN. d, Test accuracy of output results with variations in conductance values (from 1% to 20%). e, Experimental LTP characteristics. f, Reservoir computing pattern that turns a square voltage wave into nonlinear current. g, Scheme of RNN with reservoir and readout layer. h, Test accuracy of output results with the confusion matrix. i, Experimental LIF characteristics, including firing, decay and reset. j, LIF neurons with input, decay and rest. k, Scheme of SNN with rate-coded inputs and outputs. The letter P between c, g and k denotes that the three modes are roughly in the order of energy consumption reduction. l, Test accuracy of the output results with the confusion matrix.

Source data

RNN

With long positive gate pulses (2 V; duration, 0.5 s; period, 1.0 s), G remains at the demanded values (LTP; Fig. 5e), because substantial interfacial ions remain. The experimental results of LTP are used to achieve a reservoir computing system for RNN, where G of a reservoir neuron (that is, a transistor) changes in response to the input spatiotemporal signals (Fig. 5f). The original images were cut into 22 rows × 20 pixels and turned to pulse streams as the input into the reservoir, leading to the changed G. The 88 × 10-sized fully connected readout layer is trained by backpropagation (Fig. 5g). After training 60,000 images, the RNN achieves a recognition test accuracy of 87.13% (Fig. 5h).

SNN

The experimental LIF results of a transistor (Fig. 5i) are used as a neuron mimicking the membrane potential of a time series (Fig. 5j)⁵¹: V[t + 1] = wX[t] + ζV[t] – S[t]V_{th_spike}, where ζ is the decay rate of membrane potential; w is the weight matrix; X[t] is an input voltage, spike or unweighted input current; output spike S[t] is generated if V[t] > V_{th_spike}. The reset voltage is appended after each output spike. The original images were rate coded into 200 pulse patterns (each with a time step), which converts input intensity into a firing rate or spike count⁵¹ (Fig. 5k). For each neuron, the input and output are spikes. After training about 1,000 iterations (60,000 images), the SNN achieves a recognition test accuracy of 90.76% (Fig. 5l).

The above modes could be achieved based on the same multimode transistor, and therefore, a single network can switch among different modes as needed. If considering variations in device performance (Fig. 5d and Supplementary Fig. 46), 10% variations in conductance values lead to a decrease in accuracy of about 10% and 5% for ANN and RNN, respectively. Compared with the ANN, the RNN uses much fewer activated neuron-like transistors as connections by integrating calculations in the reservoirs. As the weights of inputs and connections in the reservoir are fixed, only the weights of the readout layer need to be trained, enabling the reservoir computing system to avoid some gradient-descent problems and reduce training cost^52,53,54. Although the ANN and RNN use current levels, the SNN uses sparse current spikes with high information density and consumes longer time but much lower energy cost^55,56. From a hardware application perspective, the conductance after a long time decay can be quickly refreshed by a subsecond pulse at a frequency much lower than the operation speed. Compared with other electronic devices, such as ferroelectric FETs, phase-change memory and resistive memory, the realization of various neural networks shows the potential of multimode transistor in neuromorphic computing (Supplementary Fig. 47).

Conclusions

We have reported the development of multimode transistors based on ion-dynamic capacitance. This capacitance could be described by a compact theory validated by numerical simulations. This showed that the characteristics of tunable synaptic weight, high apparent mobility, sharp subthreshold swing and memristive conductance could appear in a single transistor by programming the interfacial ion concentrations or matching the scan speed with ion motions. We then fabricated such multimode transistors using common solid-state electrolyte films, and experimentally confirmed this range of behaviours. Some of the features can also coexist to generate other characteristics including the LIF neuron. Furthermore, we showed in software that the multimode transistors can be used to create neural networks that can be switched between different modes—conventional ANNs, RNNs and SNNs —as needed.

Methods

Film characterization

Cross-sectional TEM images and energy-dispersive spectrometry maps were obtained with the JEM 2100F system operated at 200 kV, with the samples prepared on silicon using focused-ion-beam techniques. The chemical structures of AlO_x and ZrO_x films on silicon were characterized by X-ray photoelectron spectroscopy (Thermo Fisher ESCALAB 250Xi) using a monochromatized Al Kα source with a step size of 0.05 eV. All the binding energies were referenced to the C1s peak at 284.6 eV of the surface adventitious carbon. The AlO_x powders were used for the NMR experiments. The powders were prepared by drop casting appropriate precursor solutions on Si substrates at 120 °C for 2 min. This process was repeated about 40 times. Then, the samples were annealed on a hot plate at 300 or 500 °C for 30 min. The mass of the final sample is about 15 mg. The ²⁷Al NMR experiments were conducted at 600 MHz (14.1 T) on a Bruker Avance III 600 spectrometer using a 1.3 mm Bruker probe. The resonance was calibrated using Al(NO₃)₃ at 0 ppm.

Device theory

The apparent device mobility is extracted by FET characterization that contains the geometric capacitance calculated by the usually used dielectric constant C_ox: µ = L/(WV_dC_ox) × ∂I_d/∂V_g. The ratio between μ and true carrier mobility μ₀ is derived in Supplementary Note 7 and validated by numerical simulations (Supplementary Fig. 21). All the capacitance parameters including dynamic capacitance, capacitance component in the electrochemical impedance spectroscopy equivalent circuit and characteristic capacitance are summarized in Supplementary Table 5. The reversed subthreshold slope SS is calculated by SS = (∂φ_s/∂logI_d)/(1 – ∂V_ox/∂V_g), where V_ox = Q_i/C. The SS is approximated as described in Supplementary Note 8 and validated by numerical simulations (Supplementary Fig. 33). For demonstration, a transistor calculator is encoded in an HTML file with a user interface and provided in the Supplementary Information. Readers can use it to check how the main parameters affect the device operation mode.

Device simulation with technology computer-aided design

In numerical simulations, an electrolyte layer (40 nm) with mobile cations and anions (10²⁰ cm⁻³) is under an n-type semiconductor (carrier mobility μ₀ of 15 cm² V^–1 s^–1). Numerical simulations were carried out using technology computer-aided design tools (Supplementary Note 2; parameters are listed in Supplementary Table 4). The simulation of the electrolyte-gated transistors and the analysis of I–V curves, charge and ion distribution, potential and electric field are provided in the Supplementary Information.

Device fabrication

The 0.2 mol l^–1 InO_x precursor was prepared by dissolving indium nitrate hydrate in deionized water. The 0.2 mol l^–1 AlO_x (ZrO_x) precursor was prepared by dissolving aluminium nitrate hydrate (zirconium oxynitrate hydrate), nitric acid and ammonium hydroxide in hydrogen peroxide. The metal–insulator–metal capacitors were fabricated as follows. After being stirred and filtered, the AlO_x (ZrO_x) precursor was spin coated on the heavily doped silicon wafer and annealed on the hot plate at 300 °C (230 °C) for 30 min. The process was repeated five times to deposit an ~40 nm film. The Al top electrodes were deposited by thermal evaporation through a shadow mask. The AlO_x/InO_x TFTs were fabricated after the deposition of AlO_x. The InO_x precursor was spin coated on AlO_x and annealed at 230 °C for 2 h. After the photolithography process, the channel layer was patterned with a channel width of 96 μm and channel length of 24 μm. Finally, Al was deposited and lifted off to form the source and drain electrodes. Conventional TFTs were fabricated by a similar method, but AlO_x was annealed at 500 °C (Supplementary Note 12).

Device characterization

The cyclic voltammograms and I–V curves of the TFT were measured using an Agilent B1500A semiconductor parameter analyser in air and at room temperature. The sweep rate was adjusted by setting the step number and step delay time. The mobility in the linear regime and reversed SS are extracted by I_d = WµC_ox(V_g – V_th)V_d/L and SS = 1/(∂log₁₀I_d/∂V_g), respectively. The electrochemical impedance spectroscopies were measured by a Zahner electrochemical workstation. The a.c. amplitude was set as 100 mV. The potentiostatic was turned on and the d.c. voltage was set from −1 to 3 V. The frequency was set from 0.1 Hz to 1 MHz. The capacitance at 1 kHz was used to calculate the apparent mobility of TFTs. The results of varying V_g and sweep rate to obtain different apparent mobility μ or SS values in the InO_x/AlO_x and InO_x/ZrO_x transistors are shown in Supplementary Notes 7 and 8. The temperature-dependent transistor characteristics were performed in vacuum with a temperature controller. Different batches of devices were fabricated with the same process and measured. The subsecond gate pulses are generated from the DG1032Z signal generator.

Neural networks

This work was simulated in Python 3.8.12 and the codes are available via GitHub. (1) ANN. An ANN was established in the CrossSim platform⁴⁷. A three-layer backpropagation network with 784 input neurons, 300 hidden neurons and 10 output neurons was used for handwritten digit classification. Two datasets, namely, a small image (8 × 8 pixels) from the UCI Machine Learning Repository⁴⁹ and a large image (28 × 28 pixels) from the Modified National Institute of Standards and Technology database, were used to train the network, and the dataset distribution of training and testing is shown in Supplementary Table 6. With Gaussian white noise (20% standard deviation), the accuracy became 80% for large digits and 85% for small digits. (2) RNN. Schematic of the training process of the reservoir computing system is shown in Supplementary Fig. 45a. The original images were binarized first, then cut into 22 rows × 20 pixels to remove any invalid pixels. Each row was divided into four groups with each group containing five pixels; thus, the image was converted into 88 pulse streams. The reservoir layer was simulated by the LTP device model. As for the readout layer, we chose the SoftMax function $S(y_{{{\mathrm{i}}}}) = \mathrm{e}^{y_{{{\mathrm{i}}}}}/\mathop {\sum }\nolimits_{{{{k}}}} \mathrm{e}^{y_{{{{k}}}}}$ as the activation function and cross-entropy $L = - 1/N\mathop {\sum }\nolimits_{{{\mathrm{i}}}} \hat y_{{{\mathrm{i}}}}\log \left( {S_{{{\mathrm{i}}}}} \right)$ as the loss function. (3) SNN. Schematic of the training process of the SNN is shown in Supplementary Fig. 45b. Each neuron of the SNN was inspired by spike inputs and would generate spike outputs based on the LIF model. The loss function is the spike-count-based cross-entropy that the spikes at each time step are accumulated and then passed through the cross-entropy loss function. The SNN work is simulated by Python packages PyTorch and snnTorch⁵¹.