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COMPUTING-IN-MEMORY

Resistive memories stack up

Nature Electronics volume 5, pages 414–415 (2022)Cite this article

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Three-dimensional computing systems made of vertically integrated complementary metal–oxide–semiconductor circuits and layered resistive memory can perform analogue computing-in-memory with high energy efficiency.

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Fig. 1: A 3D computing-in-memory system with eight layers of vertical RRAM and 55 nm CMOS peripheral circuits.

References

  1. Verma, N. et al. IEEE Solid State Circuits Mag. 11, 43–55 (2019).

    Article  Google Scholar 

  2. Ielmini, D. & Wong, H.-S. P. Nat. Electron. 1, 333–343 (2018).

    Article  Google Scholar 

  3. Chen, W.-H. et al. Nat. Electron. 2, 420–428 (2019).

    Article  Google Scholar 

  4. Chang, M. et al. In 2022 IEEE Int. Solid-State Circ. Conf. (ISSCC) 1–3 (IEEE, 2022); https://doi.org/10.1109/ISSCC42614.2022.9731679

  5. Yin, S., Sun, X., Yu, S. & Seo, J.-S. IEEE Trans. Electron Dev. 67, 4185–4192 (2020).

    Article  Google Scholar 

  6. Luo, Q. et al. In 2017 IEEE Int. Electron Dev. Meeting (IEDM) 2.7.1–2.7.4 (IEEE, 2017); https://doi.org/10.1109/IEDM.2017.8268315

  7. Lin, P. et al. Nat. Electron. 3, 225–232 (2020).

    Article  Google Scholar 

  8. Huo, Q. et al. Nat. Electron. https://doi.org/10.1038/s41928-022-00795-x (2022).

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Authors and Affiliations

  1. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

    Injune Yeo & Jae-sun Seo

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  1. Injune Yeo
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  2. Jae-sun Seo
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Correspondence to Jae-sun Seo.

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The authors declare no competing interests.

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Yeo, I., Seo, Js. Resistive memories stack up. Nat Electron 5, 414–415 (2022). https://doi.org/10.1038/s41928-022-00804-z

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