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Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence


Artificial intelligence applications have changed the landscape of computer design, driving a search for hardware architecture that can efficiently process large amounts of data. Three-dimensional heterogeneous integration with advanced packaging technologies could be used to improve data bandwidth among sensors, memory and processors. However, such systems are limited by a lack of hardware reconfigurability and the use of conventional von Neumann architectures. Here we report stackable hetero-integrated chips that use optoelectronic device arrays for chip-to-chip communication and neuromorphic cores based on memristor crossbar arrays for highly parallel data processing. With this approach, we create a system with stackable and replaceable chips that can directly classify information from a light-based image source. We also modify this system by inserting a preprogrammed neuromorphic denoising layer that improves the classification performance in a noisy environment. Our reconfigurable three-dimensional hetero-integrated technology can be used to vertically stack a diverse range of functional layers and could provide energy-efficient sensor computing systems for edge computing applications.

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Fig. 1: Integration technologies of sensor computing systems for edge computing.
Fig. 2: Components of stackable hetero-integrated neuromorphic chips.
Fig. 3: Replaceable and stackable hetero-integrated neuromorphic chips and their robust kernel operations.
Fig. 4: Application of stackable neuromorphic chips: insertion of a denoising functional layer in a noisy environment.

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The data that support the findings of this study are available from the corresponding authors upon reasonable request.


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J.-H.K. acknowledges financial support from the Ministry of Trade, Industry and Energy (MOTIE), South Korea, under the Fostering Global Talents for Innovative Growth Program (P0008749) by the Korea Institute for Advancement of Technology (KIAT). The team at MIT acknowledge financial support from the Korea Institute of Science and Technology (KIST) through 2E31550 and the Samsung Global Research Outreach (GRO) Program.

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Authors and Affiliations



C.C. and P.L. conceived this work and designed the experiments. J.K. directed the team. C.C., H.K., P.L., M.-K.S, H.Y. and J.K. prepared the manuscript. C.C., M.-K.S., H.Y., J.M.S., J.L. and D.L. performed the device fabrication. H.K. grew the thin films for optoelectronic devices. C.C., J.-H.K. and P.L. conducted the crossbar array measurement. C.C. designed and built the optical setup. C.C. and H.Y. performed the sensor array measurement. C.C. conducted the neural network simulations and implementations using MATLAB, Python and PyTorch. C.C., S.P. and K.R. discussed the results of the neural networks simulations. All the authors contributed to the discussion and analysis of the results.

Corresponding authors

Correspondence to Huaqiang Wu, Peng Lin or Jeehwan Kim.

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Nature Electronics thanks Rui Yang and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Choi, C., Kim, H., Kang, JH. et al. Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence. Nat Electron 5, 386–393 (2022).

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