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Massively parallel probabilistic computing with sparse Ising machines


Solving computationally hard problems using conventional computing architectures is often slow and energetically inefficient. Quantum computing may help with these challenges, but it is still in the early stages of development. A quantum-inspired alternative is to build domain-specific architectures with classical hardware. Here we report a sparse Ising machine that achieves massive parallelism where the flips per second—the key figure of merit—scales linearly with the number of probabilistic bits. Our sparse Ising machine architecture, prototyped on a field-programmable gate array, is up to six orders of magnitude faster than standard Gibbs sampling on a central processing unit, and offers 5–18 times improvements in sampling speed compared with approaches based on tensor processing units and graphics processing units. Our sparse Ising machine can reliably factor semi-primes up to 32 bits and it outperforms competition-winning Boolean satisfiability solvers in approximate optimization. Moreover, our architecture can find the correct ground state, even when inexact sampling is made with faster clocks. Our problem encoding and sparsification techniques could be applied to other classical and quantum Ising machines, and our architecture could potentially be scaled to 1,000,000 or more p-bits using analogue silicon or nanodevice technologies.

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Fig. 1: Combinatorial optimization with invertible logic.
Fig. 2: Performance scaling between parallel (sIM) and serial (CPU) implementations.
Fig. 3: Exact factorization of a 32-bit number (P = 4,277,546,633) in the sIM.
Fig. 4: Performance of sIM versus competition-winning SAT solvers.
Fig. 5: Overclocked Gibbs sampling with sIM.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request.

Code availability

The computer code and problem instances used in this study are available from the corresponding authors upon reasonable request.


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We are grateful to B. M. Sutton, D. Eppens, A. Ho and M. Mohseni for useful discussions. N.A.A. is grateful to G. Eschemann for useful discussions on airhdl. We acknowledge Xilinx for the hardware support. K.Y.C. and L.T. acknowledge support from the Institute of Energy Efficiency, University of California, Santa Barbara. K.Y.C. and N.A.A. acknowledge support from the National Science Foundation through CCF 2106260. The research of A.G., M.C. and G.F. has been supported by project no. PRIN 2020LWPKH7 funded by the Italian Ministry of University and Research and by Petaspin association ( Computational facilities were purchased with funds from the National Science Foundation (CNS-1725797) and administered by the Center for Scientific Computing (CSC). The CSC is supported by the California NanoSystems Institute and the Materials Research Science and Engineering Center (MRSEC; NSF DMR 1720256) at University of California, Santa Barbara.

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Authors and Affiliations



N.A.A. and K.Y.C. conceived the idea and planned the study. N.A.A. set up the FPGA and performed the experimental measurements. A.G., N.A.A., G.F. and K.Y.C. performed the data analysis. All the authors have participated in useful discussions and in writing the manuscript.

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Correspondence to Navid Anjum Aadit, Giovanni Finocchio or Kerem Y. Camsari.

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Nature Electronics thanks Kosuke Tatsumura, Masanao Yamaoka and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary Discussion, Figs. 1–9 and Tables 1 and 2.

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Aadit, N.A., Grimaldi, A., Carpentieri, M. et al. Massively parallel probabilistic computing with sparse Ising machines. Nat Electron 5, 460–468 (2022).

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