Optimizing the Stability of FETs Based on Two-Dimensional Materials by Fermi Level Tuning

Despite the enormous progress achieved during the past decade, nanoelectronic devices based on two-dimensional (2D) semiconductors still suffer from a limited electrical stability. This limited stability has been shown to result from the interaction of charge carriers originating from the 2D semiconductors with defects in the surrounding insulating materials. The resulting dynamically trapped charges are particularly relevant in field effect transistors (FETs) and can lead to a large hysteresis, which endangers stable circuit operation. Based on the notion that charge trapping is highly sensitive to the energetic alignment of the channel Fermi-level with the defect band in the insulator, we propose to optimize device stability by deliberately tuning the channel Fermi-level. Our approach aims to minimize the amount of electrically active border traps without modifying the total number of traps in the insulator. We demonstrate the applicability of this idea by using two differently doped graphene layers in otherwise identical FETs with Al$_2$O$_3$ as a gate oxide mounted on a flexible substrate. Our results clearly show that by increasing the distance of the Fermi-level to the defect band, the hysteresis is significantly reduced. Furthermore, since long-term reliability is also very sensitive to trapped charges, a corresponding improvement in reliability is both expected theoretically and demonstrated experimentally. Our study paves the way for the construction of more stable and reliable 2D FETs in which the channel material is carefully chosen and tuned to maximize the energetic distance between charge carriers in the channel and the defect bands in the insulator employed.

stable circuit operation. Based on the notion that charge trapping is highly sensitive to the energetic alignment of the channel Fermi-level with the defect band in the insulator, we propose to optimize device stability by deliberately tuning the channel Fermi-level.
Our approach aims to minimize the amount of electrically active border traps without modifying the total number of traps in the insulator. We demonstrate the applicability of this idea by using two differently doped graphene layers in otherwise identical FETs with Al 2 O 3 as a gate oxide mounted on a flexible substrate. Our results clearly show that by increasing the distance of the Fermi-level to the defect band, the hysteresis is significantly reduced. Furthermore, since long-term reliability is also very sensitive to trapped charges, a corresponding improvement in reliability is both expected theoretically and demonstrated experimentally. Our study paves the way for the construction of more stable and reliable 2D FETs in which the channel material is carefully chosen and tuned to maximize the energetic distance between charge carriers in the channel and the defect bands in the insulator employed.
Keywords: Fermi-level tuning, field-effect transistor, oxide defects, defect bands, 2d materials, graphene, hysteresis, bias-temperature instability, reliability Two-dimensional(2D) semiconductors hold the promise of revolutionizing nanoelectronics. Their inherent atomic layer thinness makes them a plausible candidate for ultimately scaled field-effect transistors(FETs) at the end of the roadmap of silicon technology. 1 In contrast to silicon, 2D semiconductors retain sizable mobilities at thicknesses below 1 nm, 2 a thickness which would also suppress short-channel effects in FETs, thereby allowing for channel lengths L < 5 nm. 3 In addition, the flexible integration of 2D materials in van der Waals heterostructures 4 opens up new design options for highly energy efficient transistors which overcome the limitations of thermal charge carrier injection. 5 Beyond advancing modern nanoelectronics, 2D materials can be used for many other applications, from photonics and optoelectronics 6 over neuromorphic computing 7 to nano-electro-mechanical systems (NEMS), 8 radio-frequency devices, 9 Hall sensors 10 and various gas and biological sensors. 11 Overall, theoretical prospects and available prototypes indicate a bright future for 2D material based devices. Nevertheless, all application scenarios depend on the requirement that devices need to show stable operation throughout their lifetime, as defined by the stability of the threshold voltage V TH . In graphene FETs (GFETs) the threshold voltage corresponds to the charge neutrality or Dirac voltage (V Dirac ), as the gate voltage where the current is at its minimum. 12 When using FETs as switches in digital logic, the circuitry inherently relies on stable V TH of all FETs it comprises. Also applications in radio-frequency electronics rely on a stable operating point and in gas sensors for example the shift of V TH /V Dirac can serve as measurement signal, 13 thus unrelated drifts of these properties lead to measurement errors. In consequence, it is essential that FETs show minimal instabilities of the threshold voltage regardless of previous biasing, switching frequencies or temperatures.
However, stability studies on 2D FETs are scarce and typically show that their stability is at least two orders of magnitude worse 14,15 compared to silicon based FETs. 16,17 Typical measurements of FET stability are the evaluation of the hysteresis in the transfer characteristics 18 and of the stability of the threshold voltage under prolonged periods of applied elevated gate biases and temperatures, the bias temperature instability (BTI). 16 As a root cause for these phenomena early on charge trapping inside the gate oxide has been identified, 19 where, facilitated by elevated gate biases and temperatures, charges are transferred between the channel and the gate oxide in a phonon mediated transition with charging time constants spanning a wide range from ns up to years. 20 In optimized and stable silicon FETs these border traps in the gate oxide close to the channel determine the long-term stability and reliability, 17,21 but in 2D material based FETs border traps are responsible for limited device stability on shorter time scales. 22 In a first approximation, the energy levels of the defects follow a normal distribution around the average defect levels, forming defect bands, 23 as in amorphous gate oxides the local surroundings of every defect differ leading to a variation in the defects' trap levels. 24 As a consequence, the overall density of border traps and the widths of the corresponding defect bands could be considerably reduced when using crystalline insulators, such as hexagonal boron nitride (hBN) or calcium fluoride (CaF 2 ). 25 However, these insulators are difficult to synthesize and come with numerous technological challenges. For example, at the current state of the art crystalline hBN can only be grown at temperatures above 1200°C 26 and CaF 2 requires a crystalline silicon (111) substrate for growth, allowing only back-gated configurations. 27 In addition, hBN is unsuitable for use as a scaled gate insulator because of its small dielectric constant. 28 Therefore, it would be an important breakthrough if stable FETs based on 2D semiconductors could be built based on common amorphous gate oxides such as SiO 2 , Al 2 O 3 or HfO 2 .
Here, we address the need of stable 2D FETs by suggesting a novel engineering approach.
We aim to build stable 2D FETs by carefully selecting 2D materials and tuning their Fermi level (E F ) such that E F does not come near to any defect band in the amorphous gate oxide during device operation. This can be realized by careful selection of the 2D material and the amorphous gate oxide and by doping the layer to move E F to the desired location.
Our approach thus constitutes a stability-based design which targets to form a metal-oxidesemiconductor (MOS) system with a minimal amount of electrically active border traps without actually modifying the total number of traps in the insulator. We demonstrate that in this way, both electrical stability and reliability of 2D material based FETs can be improved. We apply our design method to GFETs with an aluminum oxide (Al 2 O 3 ) layer as gate oxide, where we tune E F in one batch of devices by p-doping the graphene layer, thereby validating this approach. The proposed stability-based design could act as a game changer which might allow to fabricate stable 2D material based FETs, neuromorphic memory elements and sensors in the future.

Fermi Level Tuning for Stable 2D FETs
Our stability-based design approach is based on the analysis and the design of the band diagram of the MOS system, see for example a top-gated GFET in Figure 1a which forms a MOS system out of aluminum (metal), Al 2 O 3 (oxide) and graphene (semiconductor). By cutting through the MOS stack the corresponding band diagram is obtained, as indicated by the arrow in Figure 1a to the left. Every material is characterized in this view by its electron affinity, thus the energetic distance of the conduction band edge to the vacuum level and its band gap. In the case of metals and semi-metals, the work function, the energetic distance  Figure 1a, the work function of graphene amounts to 3.9 eV, thus graphene's E F is in the middle of the Al 2 O 3 defect band. This value of E F corresponds to ndoped graphene, for example using self-assembled monolayers with amine functional groups as a substrate. 37 Due to the alignment of the graphene Fermi level within the defect band, charge traps in the oxide will frequently capture and emit charges. As the applied gate   voltage modifies the charging probabilities of the defects according to the electric field, 20 V TH depends on previous biasing and a pronounced hysteresis will be visible as well as considerable V TH drifts during prolonged periods of applied gate biases.
However, the FET stability can be tuned by moving E F down via p-doping the graphene layer, as depicted in the band diagram to the right of Figure 1a. Here, E F of graphene amounts to 5.1 eV, as achieved through p-doping for example by depositing gold nanoparticles on the graphene surface. 38 As graphene's Fermi level is located below the Al 2 O 3 defect band, charge transfer is unlikely and rare. Therefore, the oxide defects are electrically inactive, resulting in stable V TH throughout device operation, independent of applied biases. As the valence band edge of WS 2 is located below the hole trapping band in HfO 2 , a charging of oxide defects is very improbable. Therefore, for p-doped WS 2 in combination with a HfO 2 gate oxide there are no electrically active oxide traps, leading to a stable V TH during device operation. It should be noted that for 2D semiconductors the charges are always injected from the conduction or valence band edge respectively. Thus, when designing a stable n-type or p-type MOSFET suitable combination of 2D semiconductor to oxide needs to be chosen.
Possibilities for tuning the stability in the context of stability-aware device design are illustrated in Figures 1c and 1d. By doping the graphene layer, graphene's E F can be tuned within the whole grey shaded area in Figure 1c. Thus, the design freedom for stability based device design is large in graphene based FETs, and the role of SiO 2 defect bands can be reduced with an E F alignment in the middle of the two defect bands and the impacts of the Al 2 O 3 defect band can be minimized for p-doped graphene layers. For 2D semiconductors like WS 2 , the design freedom for stability aware design is smaller. In Figure 1d it is shown that either the conduction or the valence band edge can be chosen via doping. However, n-type WS 2 will presumably be electrically unstable for these three amorphous oxides and electrically stable p-type FETs could be designed using Al 2 O 3 or HfO 2 . It should be noted that small energy shifts of conduction or valence band edges can be sufficient to considerably improve device stability. In Figure 2, we used the previously de- . This small value of E T − E F predicts electrically unstable devices. In contrast, Type 2 graphene is p-doped with a higher distance of E F to E T , predicting electrically more stable FETs. In addition, the layer quality of Type 1 and Type 2 is different, revealing a higher concentration of defects in graphene in Type 2 graphene, for details see their respective Raman spectra in the SI, Figure S2.
This expression gives a p-doping density for Type 1 graphene of n 1 = 8.2 × 10 11 cm −2 and for Type 2 graphene of n 1 = 4.7 × 10 12 cm −2 , thus Type 2 graphene is more p-doped by an additional doping density of approximately 3.9 × 10 12 cm −2 . These hole densities in the graphene layers at 0 V gate voltage determine the work function via 37,49 with the Fermi velocity of graphene ν F = 1.1 × 10 6 ms −1 . In consequence, we estimate E W1 of Type 1 graphene to be 4.7 eV and E W2 of Type 2 graphene to be 0.2 eV higher at 4.9 eV.
To further analyze our model system we fabricated devices with Type 1 graphene but using thermal SiO 2 on silicon and quartz substrates instead of the flexible PI layer. In addition, the quality of the interface between graphene and Al 2 O 3 was modified by transferring single-layer CVD-grown hBN layers before the ALD deposition or by sputtering ∼ 2 nm thick aluminum as a seed layer for the Al 2 O 3 growth process. As will be seen in the discussion of these results in the SI Figure S3, the substrate primarily impacts the maximum current density whereas the quality of the interface with the Al 2 O 3 impacts device stability. (a)

T yp e 1 T yp e 2 T SC IS [1 ] T SC IS [2 ] P B T I [3 ] P B T I [4 ]
H ys t. [5 ] th is w or k O va ca nc y [6 ] A l in te rs t.    Table S1 in the SI. Based on density functional theory (DFT) calculations, this defect band can be associated with either oxygen vacancies 54,55 or aluminum interstitials. 54 We use for our study a normally distributed defect band with the mean defect level being located at E C −E T = 2.15±0.3 eV below the conduction band edge of Al 2 O 3 . The electron affinity (χ) of Al 2 O 3 , which determines the location of the conduction band edge, varies in literature. Here, we use 1.96 eV as obtained from internal photoemission measurements. 56 We use the same level as in 53  graphene is sufficient to render the V Dirac of these GFETs more stable.

Hysteresis dynamics
As the observed hysteresis depends critically on the voltage ranges used for the gate voltage sweeps, we compare the bias ranges used with ranges for various applications in Figure 5a  GFET [2] GFET [3] GFET [4] Hall sensor [5] phototransistor [6] phototransistor [7]     In fact, the band alignment shown in Figures 4c and 4d explains the larger hysteresis in Type 1 GFETs in comparison to Type 2 satisfactorily: In Type 1 GFETs biased at V Dirac , a considerable number of defects is negatively charged. If a negative voltage is applied, these defects discharge due to the band bending and thus V Dirac is shifted to more negative voltages during a slow up-sweep (Figure 5d). In Type 2 GFETs, in contrast, the Fermi level is located below the defect band at V Dirac , as its Fermi level has been shifted down by 200 meV via p-doping. Thus, most defects are neutral at the Dirac voltage. If a long time is spent with the GFET biased at negative voltages, the charge states do not change and the location of V Dirac during the up sweep is stable independent from the sweep time.
In short, the higher E T − E F of Type 2 graphene with respect to the Al 2 O 3 defect band leads to a smaller hysteresis width for large sweep ranges. In turn, the threshold voltage in Type 2 GFETs is more stable, as predicted by our stability-based design approach. At small gate bias ranges and fast hysteresis sweeps, Type 2 devices suffer from more charge trapping at the unclean interface with the Al 2 O 3 , and the hysteresis is similar or even higher in Type 2 devices compared to Type 1 (see Figures 5c and additional data in SI, Figure S4). For fast sweeps, fast traps at the unclean interface in Type 2 GFETs increase the hysteresis, giving the impression of a frequency independent hysteresis width ( Figure 5e). Type 1 GFETs exhibit a cleaner interface but a smaller E T − E F with respect to the Al 2 O 3 defects, strongly degrading the GFETs during slow sweeps. For high gate bias ranges and slow sweeps, the border traps of the Al 2 O 3 dominate device stability, thus more stable operation of Type 2 GFETs is observed. These results confirm that it is the alignment of the Al 2 O 3 defect band to graphene E W which determines the GFETs' stability and that this alignment can be deliberately tuned by doping the graphene layer.

Stability under static gate bias
For evaluating the long-term stabilty of the GFETs, we analyzed the Dirac voltage shifts (∆V Dirac ) after static elevated gate voltages (V G,high ) were applied for varying charging times (t charging ). We record the magnitude of the initial ∆V Dirac shift and monitor the recovery after the increased gate biasing period with fast I D -V G sweeps at logarithmically spaced recovery times. In Figure 6a the fast I D -V G sweeps recorded during the recovery from negative gate biasing (NBTI) at −10 V are shown.
NBTI measured by subjecting the devices to a gate bias of −10 V for increasingly long charging times is shown in Figure 6b for Type 1 GFETs and in Figure 6c for Type 2 GFETs.
As designed, the V Dirac shifts are smaller on Type 2 devices than on Type 1 devices. GFETs  As the picture of charge transfer to oxide defects in Al 2 O 3 explains these observations to full satisfaction, these results confirm our stability-based design approach, as we successfully designed Type 2 GFETs to be more stable.By p-doping Type 2 graphene, E F was moved further away from the Al 2 O 3 defect band, thus reducing the amount of charge trapping.
Interestingly, throughout all charging times the shifts on Type 1 devices do not recover whereas the shifts on Type 2 devices recover completely. The most surprising observation is that this is also true for a short time of only 1 s. This observation was confirmed when subjecting the devices to a smaller gate bias voltage of 5 V, see the SI Figure S5. Our approach holds the promise of fabricating electrically stable 2D FETs and is universally applicable to all insulators. We expect that it will lead to further improvements in the electrical stability of devices based on crystalline insulators where the impact of narrow insulator defect bands can be further reduced than in amorphous oxides. 25 Nevertheless, it remains to be clarified in future studies which levels of electrical stability can be attained with these Fermi level tuned systems based on amorphous oxides and on crystalline insulators, respectively. In addition, stability-based design relies on the knowledge about the defect bands in the oxide which is at the moment incomplete. Thus, it cannot be excluded that in parts of the oxide band gap which is at the moment thought to be free of defect bands, new defect bands might be discovered. Therefore, while the potential gains of taking the stability-based perspective into account from the beginning of the design process could be high, there are currently many unknowns related to feasibility and practicability of the suggested design paradigm which will need to be addressed in future studies.

Methods
Device fabrication: Our top-gated GFETs were fabricated on spin coated polyimide (PI) substrates using photolithography. First, the flexible substrate was prepared by spin coating PI in liquid form on a Si wafer and subsequently curing the layer. The thickness of the solidified PI film was about 8 µm. During the fabrication process, a rigid Si substrate was used as a support layer. In the next step a CVD grown graphene layer was transferred to the PI substrate. We study two batches of GFETs where the channel is formed by graphene samples purchased from different vendors, namely vendor 1 (Type 1) and vendor 2 (Type 2).
For Type 1 devices the CVD graphene was transferred from the copper growth substrate using a PMMA assisted wet transfer method, 66 for Type 2 GFETs the transfer was performed by vendor 1. The Type 1 graphene flake covered an area of 2×2 cm and was of higher quality than the Type 1 flake which covered a 6 inch wafer. The different quality of the graphene layers was confirmed by Raman spectroscopy, for details see the supporting information. The graphene layer was patterned in an oxygen plasma etch step to form channels of a length (L) of 160 µm and a width (W ) of 100 µm. In the next step, the source and drain contacts were deposited by sputtering 50 nm Ni, followed by a lift-off process. This step was followed by growing 40 nm of Al 2 O 3 with atomic layer deposition (ALD) on top of the devices to form the gate oxide in a top-gated configuration. In order to finalize the GFETs, the top-gate electrode was fabricated by sputtering 10 nm of Ti and 150 nm of Al and patterned in a lift-off process. To be able to contact source and drain pads, vias were opened through the Al 2 O 3 with wet buffered oxide etchant.
Measurement technique: Our electrical measurements were performed in vacuum at room temperature and in complete darkness. The devices were examined with the PI supported on a silicon wafer. From two-probe measurements we extracted the field-effect mobility of the GFETs and found it to be 4000 cm 2 /Vs for Type 1 graphene and 1000 cm 2 /Vs for Type 2 graphene. The Hall mobility of both samples was found to be slightly higher. The hysteresis was analyzed by measuring the double sweep I D -V G characteristics using different sweep times t sw and sweep ranges V Gminthe to V Gmax . The hysteresis width ∆V H was extracted as the difference between the forward and reverse sweep V Dirac . As was suggested in our previous work, 22 we expressed the hysteresis dynamics using the ∆V H (1/t sw ) traces. Finally, the BTI degradation/recovery dynamics were analyzed using subsequent degradation/recovery rounds with either fixed stress time t deg and increasing high voltage levels V G,high , or fixed V G,high and increasing t deg . During the recovery period we apply a constant recovery voltage of V G,recovery = 1 V between the sweeps. This voltage is chosen to be close to the charge carrier equilibrium at V Dirac . In order to avoid artifacts from fast traps charged during the sweep, the down sweep I D -V G is used to monitor the recovery of NBTI. 67 The characteristics obtained when using up sweeps to measure NBTI recovery are shown in the SI Figure S6.