Out-of-equilibrium phonons in gated superconducting switches

Recent experiments have suggested that superconductivity in metallic nanowires can be suppressed by the application of modest gate voltages. The source of this gate action has been debated and either attributed to an electric-field effect or to small leakage currents. Here we show that the suppression of superconductivity in titanium nitride nanowires on silicon substrates does not depend on the presence or absence of an electric field at the nanowire, but requires a current of high-energy electrons. The suppression is most efficient when electrons are injected into the nanowire, but similar results are obtained when electrons are passed between two remote electrodes. This is explained by the decay of high-energy electrons into phonons, which propagate through the substrate and affect superconductivity in the nanowire by generating quasiparticles. By studying the switching probability distribution of the nanowire, we also show that high-energy electron emission leads to a much broader phonon energy distribution compared with the case where superconductivity is suppressed by Joule heating near the nanowire.

Device A2 was lithographically equivalent to Device A1, shown in Fig. 1(a) of the Main Text, except for the distance d between gates 2,3 and the nanowire (d = 1 µm in Device A1 and d = 80 nm in Device A2). A false color image of Device A2 is shown in Fig. S.1, together with a simplified measurement schematic. The nanowire under study is depicted blue, the three gates red. Critical current I C and gate current I G1 as a func- ). The fact that I C was affected at higher voltages for equal gate biases V G2 = V G3 with respect to the asymmetric bias configuration (V G2 = −V G3 ) (markers) speaks against any effect linked to electric fields between gates and nanowire.

SUPPORTING INFORMATION 2: DEVICES B AND C
In the Main Text we show a summary of the measurements obtained with Devices B and C using parametric plots of I C as a function of I G1 and I G2 . Figure S.2 shows the datasets from which these parametric plots are obtained. Measurements were performed at temperatures ranging from 20 mK (blue) to 3 K (red). Gate currents are reported only for 20 mK.

SUPPORTING INFORMATION 3: REFERENCE DEVICES AFTER ADDITIONAL FABRICATION
In the Main Text we noted that devices which underwent additional fabrication steps, showed changes in some of their properties. Here we discuss this in more detail. In order to etch the trench into the Si substrate (see Fig. 2(a) of the Main Text) the entire sample was covered by a hard mask comprising a 2 nm thick Si 3 N 4 layer, grown by plasma enhanced atomic layer deposition, and a 210 nm thick SiO 2 layer grown by plasma enhanced chemical vapor deposition. Both depositions were performed at a temperature of 300 • C. After definition of the trench by electron beam lithography, reactive ion etching and inductively coupled plasma etching, the hard mask was removed by immersion in buffered HF. While the trench was etched only in Device B, additional reference devices (RDs) on this chip underwent the same deposition and etching of the hard mask. We refer to these RDs as RD 1, RD 2 and RD 3, respectively. Reference devices had a similar geometry to Device A1, with d = 1 µm, 800 nm and 400 nm, respectively. The trench in the Si substrate was etched only for Device B. All devices that underwent further processing showed a characteristic asymmetric behavior, with I C decreasing faster for I G1 < 0 than for I G1 > 0. We also found that RDs exhibited a reduced suppression efficiency for I G1 > 0. Figure S.3(b) shows a parametric plot of I C as a function of I G2 . We notice that Device A1, which did not undergo additional fabrication, showed the fastest suppression of I C . Reference Devices 1, 2 and 3 have quantitatively similar behavior, despite the fact that d varies from 400 nm to 1 µm. This is presumably due to natural sample-to-sample variations following the ad- for Devices A1 and B at various temperatures, with panels (a) to (c) summarizing the behavior as a function of V G1 , and panels (d) to (f) summarizing the behavior as a function of V G2 − V G3 . The power P 2µA , needed to reach I C = 2 µA via Gate 1, is plotted in Fig. S.4(c) as a function of temperature. As stated in the Main Text, the configuration with V G1 < 0 requires 2.5 times less power than the one with V G1 > 0 for low temperatures. We further show here that the asymmetry tends to vanish as the critical temperature is approached, with a temperature dependence reminiscent of the superconducting order parameter. Figure S.4(f) shows the temperature dependence of P 5µA , the power needed to reach I C = 5 µA via Gate 2 and 3. The green (blue) curve is for Device A1 (Device B) respectively. For Device B with a trench between remote gates and nanowire P 5µA is roughly six times larger than for Device A1, but both curves decrease with temperature similar to the situation with local gate electrodes. Figure 4 of the Main Text shows the switching probability distribution (SPD) measured in Devices A1 and C. Such measurements were performed by ramping the source drain current I SD and recording, for each sweep, the I SD value where switching from superconducting to resistive state occurred. Data was acquired for 2 × 10 4 switching events and I SD was ramped at a rate v = 6.4 mAs −1 . In Fig. S.5(a) we plot again the SPDs measured in Device A1 at zero gate voltages and at a temperature of 20 mK (blue circles) and 2.2 K (green circles). In Fig. S.5(b) we plot the switching rates (markers), obtained from the data in Fig. S.5(a) by KFD transform [1]:

SUPPORTING INFORMATION 5: FIT OF THE SWITCHING PROBABILITY DISTRIBUTION
where P is the measured switching probability. We fit to the SPD for each temperature, as shown in Fig. S.5(a), to a model for the switching rate of a superconducting nanowire [2] that follows the relation: For a nanowire forming a phase slip junction, we have κ = √ 6/2, η = 5/4 and ν = 5/8. This model accounts for switching due to macroscopic quantum tunneling (MQT) and thermally activated phase escape mechanisms, which dominate at low and high temperatures respectively. We convert the modeled switching rate Γ to a SPD using the inverse KFP transform [1]: We fit the logarithm of the probability distribution to optimally account for the shape of the SPD tails. We set T C = 3.7 K, as measured in Ref. [3], and fit with Ω 0 , I c0 and T q as free parameters. From the fit, we obtain Ω 0 = 67.5 × 10 12 rads −1 , I c0 = 45.7 µA, T q = 0.77 K. The finding of T q ≫ 20 mK confirms MQT is the dominant phase escape mechanism at low temperatures. With these parameters, one should be able to calculate the SPD at any given temperature. However, we find that the curve at T = 2.2 K is satisfactorily reproduced only by setting the parameter κ to 71% of its theoretical value, similar to previous observations [2]. The value κ = √ 6/2 was derived under the assumption of a nanowire width much larger than the superconducting coherence length [4]. This assumption might not be completely justified in the current experiment.
Alternatively to the fit, it is possible to relate the standard deviation of the switching currents σ IC to an effective energy E eff = k B T eff via the Kurkijavi power law [5]: where Φ 0 = h/2e is the flux quantum. In the Main Text we use such a relation to extract an effective temperature from the broad SPDs resulting from current injection in the nanowires.