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Logically synthesized and hardware-accelerated restricted Boltzmann machines for combinatorial optimization and integer factorization


The restricted Boltzmann machine (RBM) is a stochastic neural network capable of solving a variety of difficult tasks including non-deterministic polynomial-time hard combinatorial optimization problems and integer factorization. The RBM is ideal for hardware acceleration as its architecture is compact (requiring few weights and biases) and its simple parallelizable sampling algorithm can find the ground states of difficult problems. However, training the RBM on these problems is challenging as the training algorithm tends to fail for large problem sizes and it can be hard to find efficient mappings. Here we show that multiple, small computational modules can be combined to create field-programmable gate-array-based RBMs capable of solving more complex problems than their individually trained parts. Our approach offers a combination of developments in training, model quantization and efficient hardware implementation for inference. With our implementation, we demonstrate hardware-accelerated factorization of 16-bit numbers with high accuracy and with a speed improvement of 10,000 times over a central processing unit implementation and 1,000 times over a graphics processing unit implementation, as well as a power improvement of 30 and 7 times, respectively.

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Fig. 1: Demonstration of RBM structure and sampling algorithm.
Fig. 2: Performance on 16-bit multiplication, division and factorization.
Fig. 3: Performance of FPGA implementation versus CPU and GPU implementations with regard to factorization.
Fig. 4: Time-domain analysis of 16-bit factorization algorithm.

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Data availability

The data to reproduce Figs. 14 have been deposited in a public GitHub repository ( and on Zenodo62.

Code availability

The code to reproduce data from this work has been deposited in a public GitHub repository ( and on Zenodo62.


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This work was supported by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

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Model synthesis and analysis was performed by S.P. FPGA programming was performed by S.P. and P.C. The manuscript was co-written by S.P., P.C. and S.S. S.S. supervised the research. All the authors contributed to discussions and commented on the manuscript.

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Correspondence to Saavan Patel or Sayeef Salahuddin.

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Supplementary Figs. 1 and 2, Tables 1–3 and Discussion.

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Patel, S., Canoza, P. & Salahuddin, S. Logically synthesized and hardware-accelerated restricted Boltzmann machines for combinatorial optimization and integer factorization. Nat Electron 5, 92–101 (2022).

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