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High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon


In-memory computing can be used to overcome the von Neumann bottleneck—the need to shuffle data between separate memory and computational units—and help improve computing performance. Co-integrated vertical transistor selectors (1T) and resistive memory elements (1R) in a 1T1R configuration offer advantages of scalability, speed and energy efficiency in current mass storage applications, and such 1T1R cells could also be potentially used for in-memory computation architectures. Here we show that a vertical transistor and resistive memory can be integrated onto a single vertical indium arsenide nanowire on silicon. The approach relies on an interface between the III–V semiconductor nanowire and a high-κ dielectric (hafnium oxide), which provides an oxide layer that can operate either as a vertical transistor selector or a high-performance resistive memory. The resulting 1T1R cells allow Boolean logic operations to be implemented in a single vertical nanowire with a minimal area footprint.

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Fig. 1: Vertical III–V 1T1R structure.
Fig. 2: Electrical performance of vertical III–V 1T1R.
Fig. 3: Vertical III–V 1T1R NAND-gate implementation and device variability.
Fig. 4: XPS characterization of the interlayer oxide.

Data availability

The datasets analysed in this study are available from the corresponding authors upon reasonable request.


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We would like to thank J. Svensson for growing the nanowires for this work. This work is financed through the Swedish Research Council grant no. 2016-06186 Electronics beyond kT/q (L.-E.W.).

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Authors and Affiliations



M.S.R. fabricated the 1T1R devices. M.S.R. and K.-M.P. performed the electrical characterization of 1T1R devices. K.-M.P. fabricated the planar devices for XPS characterization. A.I. and R.T. performed the XPS characterization and prepared Fig. 4 with the corresponding analysis. K.-M.P. actively contributed to the writing process and performed the array simulations. A.J. helped with the SiO2 process module and prepared Fig. 1a. M.S.R. conceptualized the idea of the metal electrode-less RRAM integration. M.S.R. and L.-E.W. wrote the manuscript. L.-E.W. initialized and supervised the project. All the authors discussed and revised the final manuscript.

Corresponding authors

Correspondence to Mamidala Saketh Ram or Lars-Erik Wernersson.

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The authors declare no competing interests.

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Peer review information Nature Electronics thanks Cezhou Zhao and the other, anonymous, reviewer(s) for their contribution to the peer review of this work

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Supplementary Information

Supplementary Figs. 1–7 and Tables 1–4.

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Ram, M.S., Persson, KM., Irish, A. et al. High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon. Nat Electron 4, 914–920 (2021).

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