In-memory computing can be used to overcome the von Neumann bottleneck—the need to shuffle data between separate memory and computational units—and help improve computing performance. Co-integrated vertical transistor selectors (1T) and resistive memory elements (1R) in a 1T1R configuration offer advantages of scalability, speed and energy efficiency in current mass storage applications, and such 1T1R cells could also be potentially used for in-memory computation architectures. Here we show that a vertical transistor and resistive memory can be integrated onto a single vertical indium arsenide nanowire on silicon. The approach relies on an interface between the III–V semiconductor nanowire and a high-κ dielectric (hafnium oxide), which provides an oxide layer that can operate either as a vertical transistor selector or a high-performance resistive memory. The resulting 1T1R cells allow Boolean logic operations to be implemented in a single vertical nanowire with a minimal area footprint.
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The datasets analysed in this study are available from the corresponding authors upon reasonable request.
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We would like to thank J. Svensson for growing the nanowires for this work. This work is financed through the Swedish Research Council grant no. 2016-06186 Electronics beyond kT/q (L.-E.W.).
The authors declare no competing interests.
Peer review information Nature Electronics thanks Cezhou Zhao and the other, anonymous, reviewer(s) for their contribution to the peer review of this work
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Ram, M.S., Persson, KM., Irish, A. et al. High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon. Nat Electron 4, 914–920 (2021). https://doi.org/10.1038/s41928-021-00688-5
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