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Multi-channel nanowire devices for efficient power conversion


Nanowire-based devices can potentially be of use in a variety of electronic applications, from ultrascaled digital circuits to 5G communication networks. However, the devices are typically restricted to low-power applications due to the relatively low electrical conductivity and limited voltage capability of the nanowires. Here, we show that wide-band-gap AlGaN/GaN nanowires containing multiple two-dimensional electron gas channels can be used to create high-electron-mobility tri-gate transistors for power-conversion applications. The multiple channels lead to improved conductivity in the nanowires, and a three-dimensional field-plate design is used to manage the high electric field. Power devices made with 15-nm-wide nanowires are shown to exhibit low specific on resistances of 0.46 mΩ cm−2, enhancement-mode operation, improved dynamic behaviour and breakdown voltages as high as 1,300 V.

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Fig. 1: Concept of multi-channel tri-gate devices.
Fig. 2: Design of multi-channel epitaxial structures for power devices.
Fig. 3: Multi-channel tri-gate device characteristics.
Fig. 4: Achieving high breakdown voltage and low on resistance in multi-channel structures.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.


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We thank R. Soleimanzadeh and G. Santoruvo for their assistance in electrothermal and Hall measurements, and the staff in the CMi and ICMP cleanrooms at EPFL for their technical support. This work was supported in part by the European Research Council (ERC) under the European Union’s H2020 programme/ERC Grant Agreement 679425, in part by the Swiss National Science Foundation (SNSF) under Assistant Professor (AP) Energy Grants PYAPP2_166901 and 200021_169362 and in part by the ECSEL Joint Undertaking (JU) under Grant Agreement 826392. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Austria, Belgium, Germany, Italy, Norway, Slovakia, Spain, Sweden and Switzerland.

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Authors and Affiliations



E.M., L.N. and J.M. conceived the project. L.N., J.M. and C.E. fabricated the devices and performed and analysed the electrical measurements. K.C., P.X. and J.M. grew the epitaxy structures. V.T., T.-H.S. and T.W. performed and analysed the STEM measurements. E.M., L.N. and J.M. wrote the paper, and all authors approved the final version of the manuscript.

Corresponding author

Correspondence to E. Matioli.

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The authors declare no competing interests.

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Peer review information Nature Electronics thanks Kevin Chen and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data

Extended Data Fig. 1 Electron transport in multi-channel nanowires.

a, Electron mobility in multi-channel nanowires measured by gated hall bar at different gate voltages (VG) and nanowire width (wNW). The mobility peak depends on the nanowire width and shifts to higher VG as wNW decreases. b, Peak mobility as a function of wNW, extracted from figure (a). 20 nm-wide nanowires still present a high mobility value of 1200 cm2/Vs. This is of great importance as it demonstrates excellent electron conduction despite the small nanowire dimensions and the sidewalls scattering contributions. The excellent mobility results in a very low sheet resistance Rs of 150 Ω/sq for 20 nm e-mode nanowires c. Such value is half of the typical sheet resistance of conventional planar single-channel heterostructures. d, TEM cross-section showing the interface between the multi-channel nanowire and the ALD SiO2 gate oxide. A smooth surface with no evident roughness above ~ 1 nm can be observed.

Extended Data Fig. 2 Threshold voltage in multi-channel nanowires.

a, The minimum nanowire width to achieve e-mode operation was extracted by employing the conductance method. The I-V characteristics of Fat-FET with different nanowire width (wNW) was measured, from which the nanowire conductance (GNW) was extracted. By linear fit of the GNW versus wNW plot, a nanowire sidewalls depletion (wDepl) of 16.5 nm was calculated for gate voltage (VG) of 0 V. As VG increased, wDepl decreased showing the effective gate control over the nanowire. b, The depletion width indicates the minimum nanowire width to achieve e-mode operation since for wNW < 2wDepl the depletion regions from the two sidewalls merge in the center and eliminate the 2DEG. c, It should be noted that while in general a much higher gate voltage is required to turn off a multi-channel nanowire with respect to a single-channel one due to its larger carrier density, for small nanowire widths such difference becomes smaller and multi-channel devices show very similar VTH with respect to single-channel counterpart for wNW below 50 nm, despite the much larger Ns. This is due to the predominant side gate control and to the strong sidewalls depletion at such narrow widths, which is similar for multi- and single-channel nanowires. d, The evaluation of the sidewalls depletion width is consistent with the device transfer curves, which indicate 30 nm as the minimum nanowire width to achieve positive VTH. To further shift VTH to positive values, the conventional Ni-Au gate metal stack was replaced by a Pt-Au gate metal, which resulted in a threshold voltage increase of about 0.5 V. Such improvement, which is consistent for different wNW, derives from the higher work-function of Pt with respect to Ni and allows to increase VTH without any degradation of the channel, resulting in large VTH of 0.85 V for 15 nm-wide nanowires.

Extended Data Fig. 3 Threshold voltage stability.

a, Schematics of the gate lag measurement employed to determine the device VTH stability. First, the device is stressed for a time toff = 5 ms during which a quiescent gate voltage VG,q is applied to cause trapping in the gate stack. The quiescent drain voltage VD,q is 0 V to avoid any drain lag contribution or device heating. Then the gate voltage VG is set to 7 V and the drain voltage VD to 1 V for a short time ton = 5 μs, during which the drain current (ID) is measured. Trapping in the gate stack and instability of the device VTH result in a variation of the measured ID depending on the value of the applied VG,q. b, Gate lag measurement as a function of VG,q for the presented multi-channel devices, and for a reference single-channel device having similar VTH. The measured ID has been normalized to the value obtained at VG,q = 7 V, that is when the gate voltage is kept constant and thus no stress is applied. A negligible gate lag effect is observed for the multi-channel devices with a current reduction of less than 4 % in the whole measurement range, which proves their excellent VTH stability. Moreover, multi-channel devices show much-reduced gate lag with respect to the single-channel references, which instead present a current decrease of 20 % at VG,q of −3 V. Such behavior is due to the multi-channel larger carrier concentration which results in a weaker influence of the traps in the gate dielectric on the device VTH. c, VTH as a function of temperature (T) for the presented multi-channel devices. A very constant VTH behavior can be observed in the whole measurement range up to 150 °C with the device maintaining full E-mode operation and showing only a minor VTH shift of 50 mV.

Extended Data Fig. 4 Current collapse in multi-channel tri-gate HEMTs.

a, Schematics of the double pulse measurement employed to determine the device current collapse. The device is first stressed in the off-state for a time toff = 5 ms at a large quiescent drain bias VD,q, and then it is suddenly turned on for a short time ton = 50 μs during which its on-resistance is measured. b, Normalized RON,dyn as a function of VD,q for the multi-channel devices and for two different single-channel reference devices, cofabricated in the same batch, with (1) gate termination in the nanowire region and same design with respect to the multi-channel case (2) gate termination on the planar region as for conventional single-channel device architectures. All devices present a low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. Single-channel devices with the gate termination in the nanowire region show a highly degraded RON,dyn as a consequence of the increased surface area at the nanowire sidewalls, which result in more severe electron trapping during the off-state stress. This is not the case, instead, for multi-channel devices, whose much larger carrier density (Ns) and 3D structure considerably reduce the virtual gate effect due to sidewalls traps. Most importantly, multi-channel devices show very similar performance with respect to conventional single-channel devices with gate termination on the planar region, which represents the optimal architecture for such single-channel heterostructures. This demonstrates that multi-channel devices can be effectively passivated despite their 3D architecture and can provide not only outstanding DC performance but also excellent dynamic behavior.

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Nela, L., Ma, J., Erine, C. et al. Multi-channel nanowire devices for efficient power conversion. Nat Electron 4, 284–290 (2021).

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