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Scaling out Ising machines using a multi-chip architecture for simulated bifurcation

Nature Electronics volume 4, pages 208–217 (2021)Cite this article

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An Author Correction to this article was published on 27 July 2021

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Abstract

Ising machines are hardware devices that can solve ground-state search problems of Ising spin models and could be of use in solving various practical combinatorial optimization problems. However, large-scale systems have to be implemented by partitioning into subsystems that are hard to synchronize and where communication between them is difficult. Here, we report a scale-out architecture for Ising machines that provides enlarged machine sizes and enhanced processing speeds by using multiple connected chips. The architecture is based on the partitioned version of a quantum-inspired algorithm called simulated bifurcation. To maintain time consistency between multiple chips and a sufficiently small stall rate for every time-evolution step in simulated bifurcation, the architecture relies on an autonomous synchronization mechanism that is implemented in the information exchange processes between neighbouring chips and leads to scalability of computational throughput. Our eight-FPGA (field-programmable gate array) simulated bifurcation machine can obtain high-quality solutions to a 16,384-node MAX-CUT problem in 1.2 ms, which is 828 times faster than an optimized implementation of simulated annealing.

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Fig. 1: Proposed cluster architecture for the partitioned SB.
Fig. 2: Communication modules.
Fig. 3: Computation modules.
Fig. 4: Scalability of the cluster architecture for SB.
Fig. 5: Comparison of SB and simulated annealing for an all-to-all connected 16,384-node MAX-CUT problem.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

Code availability

The cluster simulator used in this work is available from the corresponding author upon reasonable request.

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Acknowledgements

We thank Y. Kaneko, Y. Hikichi and Y. Kawamata for their support.

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Authors and Affiliations

  1. Corporate Research and Development Center, Toshiba Corporation, Kawasaki, Kanagawa, Japan

    Kosuke Tatsumura, Masaya Yamasaki & Hayato Goto

Authors
  1. Kosuke Tatsumura
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  2. Masaya Yamasaki
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  3. Hayato Goto
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Contributions

K.T. and H.G. conceived the project. K.T. designed the cluster architecture. K.T. and M.Y. implemented the design with FPGAs and measured the performance. H.G. implemented and evaluated the optimized simulated annealing. K.T. analysed and evaluated the results. K.T. wrote the manuscript. All authors reviewed and edited the manuscript.

Corresponding author

Correspondence to Kosuke Tatsumura.

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Competing interests

K.T. and H.G. are inventors on two US patent applications related to this work filed by the Toshiba Corporation (no. 16/123146, filed 6 September 2018; no. 16/118646, filed 31 August 2018).

Additional information

Peer review information Nature Electronics thanks Claudio Conti, Kentaro Sano and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary information

Supplementary Information

Supplementary Figs. 1–9 and Discussion.

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Tatsumura, K., Yamasaki, M. & Goto, H. Scaling out Ising machines using a multi-chip architecture for simulated bifurcation. Nat Electron 4, 208–217 (2021). https://doi.org/10.1038/s41928-021-00546-4

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