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Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities


Carbon nanotube field-effect transistors (CNFETs) are a promising nanotechnology for the development of energy-efficient computing. Despite rapid progress, CNFETs have only been fabricated in academic or research laboratories. A critical challenge in transferring this technology to commercial manufacturing facilities is developing a suitable method for depositing nanotubes uniformly over industry-standard large-area substrates. Such a deposition method needs to be manufacturable, compatible with today’s silicon-based technologies, and provide a path to achieving systems with energy efficiency benefits over silicon. Here, we show that a deposition technique in which the substrate is submerged within a nanotube solution can address these challenges and can allow CNFETs to be fabricated within industrial facilities. By elucidating the mechanisms driving nanotube deposition, we develop process modifications to standard solution-based methods that significantly improve throughput, accelerating the deposition process by more than 1,100 times, while simultaneously reducing cost. This allows us to fabricate CNFETs in a commercial silicon manufacturing facility and high-volume semiconductor foundry. We demonstrate uniform and reproducible CNFET fabrication across industry-standard 200 mm wafers, employing the same equipment currently being used to fabricate silicon product wafers.

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Fig. 1: Characterization of the incubation method for CNT deposition.
Fig. 2: CNT density impact on CNFET-circuit energy efficiency.
Fig. 3: Methods for improving CNT deposition through incubation.
Fig. 4: Integration of CNFETs within a commercial silicon foundry.
Fig. 5: Electrical characterization of CNFETs fabricated across 200 mm substrates within a commercial silicon foundry.

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The data that support the findings of this study are available from the corresponding author upon reasonable request.


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We acknowledge support from Analog Devices Inc. (ADI), SkyWater Technology, the Defense Advanced Research Projects Agency (DARPA) Three-Dimensional System-on-Chip (3DSoC) programme (HR0011-18-3-0006) and the Air Force Research Laboratory for support. We thank S. Feindt and A. Olney from ADI and B. Ferguson from SkyWater for collaboration. We acknowledge J. Daley (MIT) for his guidance concerning helium ion microscopy, as well as the Microsystems Technology Laboratories (MTL, MIT). The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the US Government.

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Authors and Affiliations



M.D.B. led all of the research and was involved in all aspects of the work. G.H. performed the VLSI analysis. T.S., M.D.B., C.L. and M.M.S. led efforts with A.R. and M.N. to develop and transfer technology to SkyWater Foundry, and T.S., M.D.B., C.L. and M.M.S. led efforts with D.M. and S.F. to develop and transfer technology to ADI. J.H., M.D.B. and M.M.S. developed and tested the purified contaminant-free 99.99% semiconducting CNT solution. M.M.S. advised and led on all aspects of the project.

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Correspondence to Mindy D. Bishop or Max M. Shulaker.

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Supplementary Figs. 1–10, discussion and Table 1.

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Bishop, M.D., Hills, G., Srimani, T. et al. Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities. Nat Electron 3, 492–501 (2020).

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