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A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon

Nature Electronics volume 4, pages 162–170 (2021)Cite this article

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Abstract

Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III–V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies—combining both TFETs and MOSFETs—could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal–oxide–semiconductor (CMOS) platform. Here, we report a scaled III–V hybrid TFET–MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types.

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Fig. 1: Description of the MOSFET–TFET technology platform.
Fig. 2: Material and process quality assessment.
Fig. 3: Direct-current characterization of III–V TFETs and MOSFETs.
Fig. 4: Cryogenic characterization of InGaAs/GaAsSb TFETs.
Fig. 5: Scaling behaviour of III–V MOSFETs and TFETs.
Fig. 6: Benchmarking of InGaAs/GaAsSb TFET performance.

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Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work was partially funded by the European FP7 programme under grant no. 619509 (E2SWITCH) and by the Horizon 2020 programmes under grant nos. 688784 (INSIGHT) and 871764 (SEQUENCE). We acknowledge M. Sousa, Y. Baumgartner, P. Staudinger and C. Marty for helpful technical discussions and support, as well as the entire IBM BRNC operations team.

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Authors and Affiliations

  1. IBM Research Europe, Rüschlikon, Switzerland

    Clarissa Convertino, Cezar B. Zota, Heinz Schmid, Daniele Caimi, Lukas Czornomaz & Kirsten E. Moselund

  2. EPFL, Lausanne, Switzerland

    Adrian M. Ionescu

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Contributions

C.C. carried out the experiments and wrote the initial manuscript. C.B.Z. contributed to transistor fabrication and actively participated in the experimental characterization. C.C., H.S. and K.E.M. conceived the concept for the TFET integration. L.C., C.C. and C.B.Z. developed the transistor fabrication process. L.C. and D.C. developed the wafer bonding approach. C.C. developed the material epitaxial growth. K.E.M. and A.M.I. coordinated and supervised the whole work. All authors discussed the final results and revised and commented on the submitted manuscript.

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Correspondence to Clarissa Convertino.

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Convertino, C., Zota, C.B., Schmid, H. et al. A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon. Nat Electron 4, 162–170 (2021). https://doi.org/10.1038/s41928-020-00531-3

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