Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III–V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies—combining both TFETs and MOSFETs—could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal–oxide–semiconductor (CMOS) platform. Here, we report a scaled III–V hybrid TFET–MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types.
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The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.
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This work was partially funded by the European FP7 programme under grant no. 619509 (E2SWITCH) and by the Horizon 2020 programmes under grant nos. 688784 (INSIGHT) and 871764 (SEQUENCE). We acknowledge M. Sousa, Y. Baumgartner, P. Staudinger and C. Marty for helpful technical discussions and support, as well as the entire IBM BRNC operations team.
The authors declare no competing interests.
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Convertino, C., Zota, C.B., Schmid, H. et al. A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon. Nat Electron 4, 162–170 (2021). https://doi.org/10.1038/s41928-020-00531-3