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A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon


Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III–V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies—combining both TFETs and MOSFETs—could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal–oxide–semiconductor (CMOS) platform. Here, we report a scaled III–V hybrid TFET–MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types.

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Fig. 1: Description of the MOSFET–TFET technology platform.
Fig. 2: Material and process quality assessment.
Fig. 3: Direct-current characterization of III–V TFETs and MOSFETs.
Fig. 4: Cryogenic characterization of InGaAs/GaAsSb TFETs.
Fig. 5: Scaling behaviour of III–V MOSFETs and TFETs.
Fig. 6: Benchmarking of InGaAs/GaAsSb TFET performance.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.


  1. De, V., Vangal, S. & Krishnamurthy, R. Near threshold voltage (NTV) computing: computing in the dark silicon era. IEEE Des. Test 34, 24–30 (2016).

    Article  Google Scholar 

  2. Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).

    Article  Google Scholar 

  3. Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).

    Article  Google Scholar 

  4. Ionescu, A. M. Negative capacitance gives a positive boost.Nat. Nanotechnol. 13, 7–8 (2018).

    Article  Google Scholar 

  5. Salvatore, G. A., Bouvet, D. & Ionescu, A. M. Demonstration of subthreshold swing smaller than 60mV/decade in Fe-FET with P (VDF-TrFE)/ SiO2 gate stack. Nano 8, 479–481 (2008).

    Google Scholar 

  6. Si, M. et al. Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nat. Nanotechnol. 13, 14–28 (2017).

    Google Scholar 

  7. Chen, F. et al. Integrated circuit design with NEM relays. In 2008 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD 750–757 (IEEE, 2008).

  8. Gopalakrishnan, K., Woo, R., Jungemann, C., Griffin, P. B. & Plummer, J. D. Impact ionization MOS (I-MOS)—Part II: experimental results. IEEE Trans. Electron Devices 52, 77–84 (2005).

    Article  Google Scholar 

  9. Abelein, U. et al. A novel vertical impact ionisation MOSFET (I-MOS) concept. In Proc. 2006 25th International Conference on Microelectronics, MIEL 2006 127–130 (IEEE, 2006).

  10. Avci, U. E., Morris, D. H. & Young, I. A. Tunnel field-effect transistors: prospects and challenges. IEEE J. Electron Devices Soc. 3, 88–95 (2015).

    Article  Google Scholar 

  11. Webster, J. G., Verreck, D., Groeseneken, G. & Verhulst, A. in Wiley Encyclopedia of Electrical and Electronics Engineering 1–24 (John Wiley & Sons, 2016);

  12. Seabaugh, B. A. C. & Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010).

    Article  Google Scholar 

  13. Choi, W. Y., Park, B., Lee, J. D. & Liu, T. K. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007).

    Article  Google Scholar 

  14. Jeon, K. et al. Si tunnel transistors with a novel silicided source and 46 mV/dec swing. In Symposium on VLSI Technology Digest of Technical Papers 121–122 (IEEE, 2010).

  15. Knoll, L. et al. Inverters with strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Device Lett. 34, 813–815 (2013).

    Article  Google Scholar 

  16. del Alamo, J. A. Nanometre-scale electronics with III–V compound semiconductors. Nature 479, 317–323 (2011).

    Article  Google Scholar 

  17. Sant, S. & Schenk, A. Trap-tolerant device geometry for InAs/Si pTFETs. IEEE Electron Device Lett. 38, 1363–1366 (2017).

    Article  Google Scholar 

  18. Sant, S. et al. Lateral InAs/Si p-type tunnel FETs integrated on Si—Part 2: simulation study of the impact of interface traps. IEEE Trans. Electron Devices 63, 4240–4247 (2016).

    Article  Google Scholar 

  19. Kim, D. et al. Low power circuit design based on heterojunction tunneling transistors (HETTs). In Proc. International Symposium on Low Power Electronics and Design 219–224 (ACM Press, 2009).

  20. Young, I. A., Avci, U. E. & Morris, D. H. Tunneling field effect transistors: device and circuit considerations for energy efficient logic opportunities. In Proc. 2015 IEEE International Electron Devices Meeting (IEDM) 22.1.1–22.1.4 (IEEE, 2015);

  21. Saripalli, V., Mishra, A., Datta, S. & Narayanan, V. An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. In Proc. 2011 48th ACM/EDAC/IEEE Design Automation Conference 729–734 (IEEE, 2011);

  22. Memisevic, E., Svensson, J., Hellenbrand, M., Lind, E. & Wernersson, L. E. Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 µA/µm for Ioff = 1 nA/µm at VDS = 0.3 V. In Proc. IEEE International Electron Devices Meeting 19.1.1–19.1.4 (IEEE, 2016);

  23. Alian, A. et al. InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature. Appl. Phys. Lett. 109, 243502 (2016).

    Article  Google Scholar 

  24. Zota, C. B. et al. High performance quantum well InGaAs-On-Si MOSFETs with sub-20 nm gate length for RF applications. In Proc. 2018 IEEE International Electron Devices Meeting (IEDM) 39.4.1–39.4.4 (IEEE, 2018);

  25. Zota, C. B. et al. InGaAs-on-insulator MOSFETs featuring scaled logic devices and record RF performance. In 2018 Symposium on VLSI Technology Digest of Technical Papers 165–166 (IEEE, 2018).

  26. Czornomaz, L. et al. Co-integration of InGaAs n- and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates. In Proc. 2013 International Electron Devices Meeting 2.8.1–2.8.4 (IEEE, 2013);

  27. Cutaia, D. et al. Complementary III–V heterojunction lateral NW Tunnel FET technology on Si. In 2016 Symposium on VLSI Technology Digest of Technical Papers 1–2 (IEEE, 2016).

  28. Convertino, C. et al. Sub-thermionic scalable III–V tunnel field-effect transistors integrated on Si (100). In Proc. 2019 IEEE International Electron Devices Meeting (IEDM) 37.1.1–37.1.4 (IEEE, 2019).

  29. Gopireddy, B., Skarlatos, D., Zhu, W. & Torrellas, J. HetCore: TFET-CMOS hetero-device architecture for CPUs and GPUs. In Proc. 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) 802–815 (IEEE, 2018);

  30. Convertino, C., Zota, C. B., Schmid, H., Ionescu, A. M. & Moselund, K. E. III–V heterostructure tunnel field-effect transistor. J. Phys. Condens. Matter 30, 264005 (2018).

    Article  Google Scholar 

  31. Alian, A. et al. Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs. In 2018 Symposium on VLSI Technology Digest of Technical Papers 133–134 (IEEE, 2018).

  32. Smets, Q. et al. Calibration of the effective tunneling bandgap in GaAsSb/InGaAs for improved TFET performance prediction. IEEE Trans. Electron Devices 63, 4248–4254 (2016).

    Article  Google Scholar 

  33. Convertino, C. et al. InGaAs-on-insulator FinFETs with reduced off-current and record performance. In Proc. 2018 IEEE International Electron Devices Meeting (IEDM) 39.2.1–39.2.4 (IEEE, 2018);

  34. Daix, N. et al. Towards large size substrates for III–V co-integration made by direct wafer bonding on Si. APL Mater. 2, 086104 (2014).

    Article  Google Scholar 

  35. Lin, J., Zhao, X., Antoniadis, D. A. & del Alamo, J. A. A novel digital etch technique for deeply scaled III–V MOSFETs. IEEE Electron Device Lett. 35, 440–442 (2014).

    Article  Google Scholar 

  36. Convertino, C. et al. High performance InGaAs FinFETs with raised source/drain extensions. Jpn. J. Appl. Phys. 58, 080901 (2019).

    Article  Google Scholar 

  37. Rosca, T., Saeidi, A., Memisevic, E., Wernersson, L. E. & Ionescu, A. M. An experimental study of heterostructure tunnel FET nanowire arrays: digital and analog figures of merit from 300 K to 10 K. In Proc. 2018 IEEE International Electron Devices Meeting (IEDM) 13.5.1–13.5.4 (IEEE, 2019).

  38. Ganjipour, B. et al. High current density Esaki tunnel diodes based on GaSb-InAsSb heterostructure nanowires. Nano Lett. 11, 4222–4226 (2011).

    Article  Google Scholar 

  39. Agarwal, S. & Yablonovitch, E. Band-edge steepness obtained from Esaki/backward diode current—voltage characteristics. IEEE Trans. Electron Devices 61, 1488–1493 (2014).

    Article  Google Scholar 

  40. Memisevic, E., Lind, E., Hellenbrand, M., Svensson, J. & Wernersson, L.-E. Impact of band-tails on the subthreshold swing of III–V tunnel field-effect transistor. IEEE Electron Device Lett. 3106, 1 (2017).

    Google Scholar 

  41. Sajjad, R. N., Chern, W., Hoyt, J. L. & Antoniadis, D. A. Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs. IEEE Trans. Electron Devices 63, 4380–4387 (2016).

    Article  Google Scholar 

  42. Schenk, A. et al. The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs. In Proc. 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 273–276 (IEEE, 2017).

  43. Alian, A. et al. InGaAs tunnel FET with sub-nanometer EOT and sub-60-mV/dec sub-threshold swing at room temperature. Appl. Phys. Lett. 109, 243502 (2016).

    Article  Google Scholar 

  44. Bessire, C. D. et al. Trap-assisted tunneling in Si-InAs nanowire heterojunction tunnel diodes. Nano Lett. 11, 4195–4199 (2011).

    Article  Google Scholar 

  45. Verhulst, A. S., Vandenberghe, W. G., Maex, K. & Groeseneken, G. Tunnel field-effect transistor without gate-drain overlap. Appl. Phys. Lett. 91, 053102 (2007).

    Article  Google Scholar 

  46. Le Royer, C. & Mayer, F. Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture. In Proc. 10th International Conference on Ultimate Integration of Silicon 53–56 (IEEE, 2009);

  47. Appenzeller, J. et al. Toward nanowire electronics. IEEE Trans. Electron Devices 55, 2827–2845 (2008).

    Article  Google Scholar 

  48. Zhao, X., Member, S., Vardi, A. & Alamo, J. A. Sub-thermal subthreshold characteristics in top–down InGaAs/InAs heterojunction vertical nanowire tunnel FETs. IEEE Electron Device Lett. 38, 855–858 (2017).

    Article  Google Scholar 

  49. Noguchi, M. et al. High Ion/Ioff and low subthreshold slope planar-type InGaAs tunnel FETs with Zn-diffused source junctions. In 2013 IEEE International Electron Devices Meeting (IEEE, 2013);

  50. Dewey, G. et al. Fabrication, characterization and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing. Tech. Dig. IEDM 3, 785–788 (2011).

    Google Scholar 

  51. Convertino, C., Zota, C. B., Caimi, D., Sousa, M. & Czornomaz, L. InGaAs FinFETs 3-D sequentially integrated on FDSOI Si CMOS with record perfomance. IEEE J. Electron Devices Soc. 7, 1170–1174 (IEEE, 2019);

  52. Ahn, D. H., Ji, S. M., Takenaka, M. & Takagi, S. Performance improvement of InxGa1−xAs tunnel FETs with quantum well and EOT scaling. In 2016 IEEE Symposium on VLSI Technology (IEEE, 2016);

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This work was partially funded by the European FP7 programme under grant no. 619509 (E2SWITCH) and by the Horizon 2020 programmes under grant nos. 688784 (INSIGHT) and 871764 (SEQUENCE). We acknowledge M. Sousa, Y. Baumgartner, P. Staudinger and C. Marty for helpful technical discussions and support, as well as the entire IBM BRNC operations team.

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Authors and Affiliations



C.C. carried out the experiments and wrote the initial manuscript. C.B.Z. contributed to transistor fabrication and actively participated in the experimental characterization. C.C., H.S. and K.E.M. conceived the concept for the TFET integration. L.C., C.C. and C.B.Z. developed the transistor fabrication process. L.C. and D.C. developed the wafer bonding approach. C.C. developed the material epitaxial growth. K.E.M. and A.M.I. coordinated and supervised the whole work. All authors discussed the final results and revised and commented on the submitted manuscript.

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Correspondence to Clarissa Convertino.

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Convertino, C., Zota, C.B., Schmid, H. et al. A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon. Nat Electron 4, 162–170 (2021).

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