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Two-dimensional transistors with reconfigurable polarities for secure circuits


Security is a critical aspect in modern circuit design, but research into hardware security at the device level is rare as it requires modification of existing technology nodes. With the increasing challenges facing the semiconductor industry, interest in out-of-the-box security solutions has grown, even if this implies introducing novel materials such as two-dimensional layered semiconductors. Here, we show that high-performance, low-voltage, two-dimensional black phosphorus field-effect transistors (FETs) that have reconfigurable polarities are suitable for hardware security applications. The transistors can be dynamically switched between p-FET and n-FET operation through electrostatic gating and can achieve on–off ratios of 105 and subthreshold swings of 72 mV dec−1 at room temperature. Using the transistors, we create inverters that exhibit gains of 33.3 and are fully functional at a supply voltage of 0.2 V. We also create a security primitive circuit with polymorphic NAND/NOR obfuscation functionality with sub-1-V operation voltages, and the robustness of the polymorphic gate against power supply variations is tested using Monte Carlo simulations.

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Fig. 1: Schematic of a secure chip enabled by reconfigurable FETs.
Fig. 2: Design consideration for reconfigurable Schottky-barrier FET.
Fig. 3: Black phosphorus transistors with reconfigurable polarities.
Fig. 4: Inverter characteristics.
Fig. 5: Demonstration of NAND/NOR and XOR/XNOR polymorphic gates.
Fig. 6: Robustness of the NAND/NOR and XOR/XNOR polymorphic gates to power supply variations.

Data availability

The data that support the findings within this paper are available from the corresponding author upon reasonable request.

Code availability

The computer code used in this study is available from the corresponding author upon reasonable request.


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Funding for this research was provided by the Indiana Innovation Institute and Lilly Endowment, Inc.

Author information




P.W. and J.A. conceived the idea and designed the experiments. P.W. performed device fabrication and characterization under J.A.’s supervision. D.R. and X.S.H. developed the device model and performed the circuit simulation. P.W. and J.A. wrote the manuscript with inputs from D.R. and X.S.H. All authors contributed to discussions about the manuscript.

Corresponding author

Correspondence to Joerg Appenzeller.

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The authors declare no competing interests.

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Supplementary Information

Supplementary Sections 1–8 and Figs. 1–10.

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Wu, P., Reis, D., Hu, X.S. et al. Two-dimensional transistors with reconfigurable polarities for secure circuits. Nat Electron 4, 45–53 (2021).

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