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Two-dimensional transistors with reconfigurable polarities for secure circuits

Abstract

Security is a critical aspect in modern circuit design, but research into hardware security at the device level is rare as it requires modification of existing technology nodes. With the increasing challenges facing the semiconductor industry, interest in out-of-the-box security solutions has grown, even if this implies introducing novel materials such as two-dimensional layered semiconductors. Here, we show that high-performance, low-voltage, two-dimensional black phosphorus field-effect transistors (FETs) that have reconfigurable polarities are suitable for hardware security applications. The transistors can be dynamically switched between p-FET and n-FET operation through electrostatic gating and can achieve on–off ratios of 105 and subthreshold swings of 72 mV dec−1 at room temperature. Using the transistors, we create inverters that exhibit gains of 33.3 and are fully functional at a supply voltage of 0.2 V. We also create a security primitive circuit with polymorphic NAND/NOR obfuscation functionality with sub-1-V operation voltages, and the robustness of the polymorphic gate against power supply variations is tested using Monte Carlo simulations.

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Fig. 1: Schematic of a secure chip enabled by reconfigurable FETs.
Fig. 2: Design consideration for reconfigurable Schottky-barrier FET.
Fig. 3: Black phosphorus transistors with reconfigurable polarities.
Fig. 4: Inverter characteristics.
Fig. 5: Demonstration of NAND/NOR and XOR/XNOR polymorphic gates.
Fig. 6: Robustness of the NAND/NOR and XOR/XNOR polymorphic gates to power supply variations.

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Data availability

The data that support the findings within this paper are available from the corresponding author upon reasonable request.

Code availability

The computer code used in this study is available from the corresponding author upon reasonable request.

References

  1. Novoselov, K. S. et al. Two-dimensional atomic crystals. Proc. Natl Acad. Sci. USA 102, 10451–10453 (2005).

    Article  Google Scholar 

  2. Das, S., Chen, H. Y., Penumatcha, A. V. & Appenzeller, J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 13, 100–105 (2013).

    Article  Google Scholar 

  3. Das, S. & Appenzeller, J. WSe2 field effect transistors with enhanced ambipolar characteristics. Appl. Phys. Lett. 103, 103501 (2013).

    Article  Google Scholar 

  4. Liu, H. et al. Phosphorene: an unexplored 2D semiconductor with a high hole mobility. ACS Nano 8, 4033–4041 (2014).

    Article  Google Scholar 

  5. Li, L. et al. Black phosphorus field-effect transistors. Nat. Nanotechnol. 9, 372–377 (2014).

    Article  Google Scholar 

  6. Wu, P. et al. Complementary black phosphorus tunneling field-effect transistors. ACS Nano 13, 377–385 (2019).

    Article  Google Scholar 

  7. Penumatcha, A. V., Salazar, R. B. & Appenzeller, J. Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model. Nat. Commun. 6, 8948 (2015).

    Article  Google Scholar 

  8. Robbins, M. C. & Koester, S. J. Black phosphorus p- and n-MOSFETs with electrostatically doped contacts. IEEE Electron Device Lett. 38, 285–288 (2017).

    Article  Google Scholar 

  9. Tosun, M. et al. High-gain inverters based on WSe2 complementary field-effect transistors. ACS Nano 8, 4948–4953 (2014).

    Article  Google Scholar 

  10. Schulman, D. S., Arnold, A. J. & Das, S. Contact engineering for 2D materials and devices. Chem. Soc. Rev. 47, 3037–3058 (2018).

    Article  Google Scholar 

  11. Prakash, A., Ilatikhameneh, H., Wu, P. & Appenzeller, J. Understanding contact gating in Schottky barrier transistors from 2D channels. Sci. Rep. 7, 12596 (2017).

    Article  Google Scholar 

  12. Moore, G. E. Cramming more components onto integrated circuits. Proc. IEEE https://doi.org/10.1109/JPROC.1998.658762 (1998).

  13. Franklin, A. D. Nanomaterials in transistors: from high-performance to thin-film applications. Science 349, aab2750 (2015).

    Article  Google Scholar 

  14. Skotnicki, T., Hutchby, J. A., King, T. J., Wong, H. S. P. & Boeuf, F. The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Devices Mag. https://doi.org/10.1109/MCD.2005.1388765 (2005).

  15. Rabaey, J. M., Chandrakasan, A. & Nikolic, B. Digital Integrated Circuits 2nd edn (Pearson, 2003).

  16. Servanton, G. et al. Advanced TEM characterization for the development of 28–14-nm nodes based on fully-depleted silicon-on-insulator technology. J. Phys. Conf. Ser. 471, 012026 (2013).

    Article  Google Scholar 

  17. Holler, M. et al. Three-dimensional imaging of integrated circuits with macro- to nanoscale zoom. Nat. Electron. 2, 464–470 (2019).

    Article  Google Scholar 

  18. Holler, M. et al. High-resolution non-destructive three-dimensional imaging of integrated circuits. Nature 543, 402–406 (2017).

    Article  Google Scholar 

  19. Wu, P. & Appenzeller, J. Toward CMOS like devices from two-dimensional channel materials. APL Mater. 7, 100701 (2019).

    Article  Google Scholar 

  20. Cowley, A. M. & Sze, S. M. Surface states and barrier height of metal–semiconductor systems. J. Appl. Phys. 36, 3212–3220 (1965).

    Article  Google Scholar 

  21. Appenzeller, J., Zhang, F., Das, S. & Knoch, J. in 2D Materials for Nanoelectronics (eds Houssa, M. et al.) Ch. 8, 207–240 (Taylor & Francis, 2016).

  22. Nakaharai, S. et al. Electrostatically reversible polarity of ambipolar α-MoTe2 transistors. ACS Nano 6, 5976–5983 (2015).

    Article  Google Scholar 

  23. Yu, W. J. et al. Adaptive logic circuits with doping-free ambipolar carbon nanotube transistors. Nano Lett. 9, 1401–1405 (2009).

    Article  Google Scholar 

  24. Lin, Y. F. et al. Ambipolar MoTe2 transistors and their applications in logic circuits. Adv. Mater. 26, 3263–3269 (2014).

    Article  Google Scholar 

  25. Ren, Y. et al. Recent advances in ambipolar transistors for functional applications. Adv. Funct. Mater. 29, 1–65 (2019).

    Google Scholar 

  26. Resta, G. V. et al. Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors. ACS Nano 12, 7039–7047 (2018).

    Article  Google Scholar 

  27. Bi, Y. et al. Enhancing hardware security with emerging transistor technologies. In Proc. 2016 International Great Lakes Symposium on VLSI, GLSVLSI, 305–310 (IEEE, 2016).

  28. Rajendran, J. et al. Nano meets security: exploring nanoelectronic devices for security applications. Proc. IEEE 103, 829–849 (2015).

    Article  Google Scholar 

  29. Patnaik, S. et al. Advancing hardware security using polymorphic and stochastic spin-Hall effect devices. In Proc. 2018 Conference on Design, Automation and Test in Europe Conference and Exhibition (DATE) 97–102 (IEEE, 2018).

  30. Bi, Y. et al. Emerging technology-based design of primitives for hardware security. J. Emerg. Technol. Comput. Syst. 13, 3 (2016).

    Article  Google Scholar 

  31. Dupuis, S. & Flottes, M.-L. Logic locking: a survey of proposed methods and evaluation metrics. J. Electron. Test. 35, 273–291 (2019).

    Article  Google Scholar 

  32. Roy, J. A., Koushanfar, F. & Markov, I. L. EPIC: ending piracy of integrated circuits. In Proc. Conference on Design, Automation and Test in Europe (DATE) 1069–1074 (IEEE, 2008).

  33. Plaza, S. M. & Markov, I. L. Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34, 961–971 (2015).

    Article  Google Scholar 

  34. Rajendran, J., Sinanoglu, O. & Karri, R. VLSI testing based security metric for IC camouflaging. In 2013 IEEE International Test Conference (ITC) https://doi.org/10.1109/TEST.2013.6651879 (IEEE, 2013).

  35. Rajendran, J., Sam, M., Sinanoglu, O. & Karri R. Security analysis of integrated circuit camouflaging. In Proc. 2013 ACM SIGSAC Conference on Computer and Communications Security 709–720 (ACM, 2013).

  36. Shiozaki, M., Hori, R. & Fujino, T. Diffusion programmable device: the device to prevent reverse engineering. IACR Cryptol. ePrint Arch. 2014, 109 (2014).

    Google Scholar 

  37. Malik, S., Becker, G. T., Paar, C. & Burleson, W. P. Development of a layout-level hardware obfuscation tool. In Proc. 2015 IEEE Computer Society Annual Symposium on VLSI 204–209 (IEEE, 2015).

  38. Sze, S. M. & Ng, K. K. Physics of Semiconductor Devices (Wiley, 2006).

  39. Heinzig, A., Slesazeck, S., Kreupl, F., Mikolajick, T. & Weber, W. M. Reconfigurable silicon nanowire transistors. Nano Lett. 12, 119–124 (2012).

    Article  Google Scholar 

  40. Heinzig, A., Mikolajick, T., Trommer, J., Grimm, D. & Weber, W. M. Dually active silicon nanowire transistors and circuits with equal electron and hole transport. Nano Lett. 13, 4176–4181 (2013).

    Article  Google Scholar 

  41. De Marchi, M. et al. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs. Tech. Dig. Int. Electron Devices Meet. 8.4.1–8.4.4 (2012).

  42. Larentis, S. et al. Reconfigurable complementary monolayer MoTe2 field-effect transistors for integrated circuits. ACS Nano 11, 4832–4839 (2017).

    Article  Google Scholar 

  43. Bao, R. et al. Multiple-Vt solutions in nanosheet technology for high performance and low power applications. In Proc. 2019 IEEE International Electron Devices Meeting 234–237 (IEEE, 2019).

  44. Qiao, J., Kong, X., Hu, Z. X., Yang, F. & Ji, W. High-mobility transport anisotropy and linear dichroism in few-layer black phosphorus. Nat. Commun. 5, 4475 (2014).

    Article  Google Scholar 

  45. Cai, Y., Zhang, G. & Zhang, Y. W. Layer-dependent band alignment and work function of few-layer phosphorene. Sci. Rep. 4, 6677 (2014).

    Article  Google Scholar 

  46. Haratipour, N., Namgung, S., Oh, S.-H. & Koester, S. J. Fundamental limits on the subthreshold slope in Schottky source/drain black phosphorus field-effect transistors. ACS Nano 10, 3791–3800 (2016).

    Article  Google Scholar 

  47. Haratipour, N. et al. High-performance black phosphorus MOSFETs using crystal orientation control and contact engineering. IEEE Electron Device Lett. 38, 685–688 (2017).

    Article  Google Scholar 

  48. Das, S., Demarteau, M. & Roelofs, A. Ambipolar phosphorene field effect transistor. ACS Nano 8, 11730–11738 (2014).

    Article  Google Scholar 

  49. Liu, Y. & Ang, K. W. Monolithically integrated flexible black phosphorus complementary inverter circuits. ACS Nano 11, 7416–7423 (2017).

    Article  Google Scholar 

  50. Kirsch, P. D. et al. Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning. Appl. Phys. Lett. 92, 092901 (2008).

    Article  Google Scholar 

  51. Kocher, P., Jaffe, J. & Jun, B. Differential power analysis. Proc. CRYPTO 99, 388–397 (1999).

    MATH  Google Scholar 

Download references

Acknowledgements

Funding for this research was provided by the Indiana Innovation Institute and Lilly Endowment, Inc.

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P.W. and J.A. conceived the idea and designed the experiments. P.W. performed device fabrication and characterization under J.A.’s supervision. D.R. and X.S.H. developed the device model and performed the circuit simulation. P.W. and J.A. wrote the manuscript with inputs from D.R. and X.S.H. All authors contributed to discussions about the manuscript.

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Correspondence to Joerg Appenzeller.

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Supplementary Information

Supplementary Sections 1–8 and Figs. 1–10.

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Wu, P., Reis, D., Hu, X.S. et al. Two-dimensional transistors with reconfigurable polarities for secure circuits. Nat Electron 4, 45–53 (2021). https://doi.org/10.1038/s41928-020-00511-7

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