A ferroelectric semiconductor field-effect transistor

Abstract

Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are potentially of use in non-volatile memory technology, but they suffer from short retention times, which limits their wider application. Here, we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, room-temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers and its potential for large-area growth. A passivation method based on the atomic layer deposition of aluminium oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on current of 862 μA μm−1 and a low supply voltage.

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Fig. 1: Schematic diagram and proposal for a ferroelectric semiconductor field-effect transistor (FeS-FET).
Fig. 2: Material properties of the ferroelectric semiconductor α-In2Se3.
Fig. 3: PFM measurement on an α-In2Se3 thin film.
Fig. 4: Switching characteristics of α-In2Se3 FeS-FETs.
Fig. 5: Simulation of α-In2Se3 FeS-FETs.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request. Raw data for the PFM measurements are provided in the Supplementary Information.

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Acknowledgements

This work was supported in part by a NSF/AFOSR EFRI 2DARE programme and in part by ASCENT, one of six centres in JUMP, a Semiconductor Research Corporation (SRC) programme sponsored by DARPA. J.J. and H.W. acknowledge support from the US Office of Naval Research for the TEM effort at Purdue.

Author information

P.D.Y. and M.S. conceived the idea and proposed the FeS-FET concept. M.S. carried out device fabrication, electrical measurements and analysis. A.K.S. and S.K.G. performed the numerical simulation. S.G. and W.W. performed PFM measurements. J.Q., J.J. and H.W. conducted the TEM and EDS measurements. Y.D. and M.S. carried out SEM imaging and EDS analysis. G.Q. obtained the Raman and photoluminescence measurements. G.Q. and C.N. performed the low-temperature IV and Hall measurements. M.S. and P.D.Y. co-wrote the manuscript and all authors commented on it.

Correspondence to Peide D. Ye.

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Supplementary information

Supplementary Information

Supplementary sections 1–8.

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Si, M., Saha, A.K., Gao, S. et al. A ferroelectric semiconductor field-effect transistor. Nat Electron 2, 580–586 (2019). https://doi.org/10.1038/s41928-019-0338-7

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