Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

A ferroelectric semiconductor field-effect transistor

Nature Electronics volume 2, pages 580–586 (2019)Cite this article

Subjects

Abstract

Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are potentially of use in non-volatile memory technology, but they suffer from short retention times, which limits their wider application. Here, we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, room-temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers and its potential for large-area growth. A passivation method based on the atomic layer deposition of aluminium oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on current of 862 μA μm−1 and a low supply voltage.

Access options

Rent or Buy article

Get time limited or full article access on ReadCube.

from$8.99

Rent or Buy

All prices are NET prices.

Fig. 1: Schematic diagram and proposal for a ferroelectric semiconductor field-effect transistor (FeS-FET).
Fig. 2: Material properties of the ferroelectric semiconductor α-In2Se3.
Fig. 3: PFM measurement on an α-In2Se3 thin film.
Fig. 4: Switching characteristics of α-In2Se3 FeS-FETs.
Fig. 5: Simulation of α-In2Se3 FeS-FETs.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request. Raw data for the PFM measurements are provided in the Supplementary Information.

References

  1. 1.

    Miller, S. L. & McWhorter, P. J. Physics of the ferroelectric nonvolatile memory field effect transistor. J. Appl. Phys. 72, 5999–6010 (1992).

    Article  Google Scholar 

  2. 2.

    Ishiwara, H. Current status and prospects of FET-type ferroelectric memories. J. Semicond. Technol. Sci. 1, 1–14 (2001).

    Google Scholar 

  3. 3.

    Ishiwara, H. FeFET and ferroelectric random access memories. J. Nanosci. Nanotechnol. 12, 7619–7627 (2012).

    Article  Google Scholar 

  4. 4.

    Müller, J. et al. Nanosecond polarization switching and long retention in a novel MFIS-FET based on ferroelectric HfO2. IEEE Electron Device Lett. 33, 185–187 (2012).

    Article  Google Scholar 

  5. 5.

    Yurchuk, E. et al. Origin of the endurance degradation in the novel HfO2-based 1T ferroelectric non-volatile memories. In IEEE International Reliability Physics Symposium 2E.5.1–2E.5.5 (IEEE, 2014).

  6. 6.

    Yurchuk, E. et al. Charge-trapping phenomena in HfO2-based FeFET-type nonvolatile memories. IEEE Trans. Electron Devices 63, 3501–3507 (2016).

    Article  Google Scholar 

  7. 7.

    Muller, J. et al. High endurance strategies for hafnium oxide based ferroelectric field effect transistor. In 2016 16th Non-Volatile Memory Technology Symposium (NVMTS) 7781517 (IEEE, 2016).

  8. 8.

    Chung, W., Si, M. & Ye, P. D. Hysteresis-free negative capacitance germanium CMOS FinFETs with bi-directional sub-60 mV/dec. In Proceedings of IEEE International Electron Devices Meeting 365–368 (IEEE, 2017).

  9. 9.

    Chung, W. et al. First direct experimental studies of Hf0.5Zr0.5O2 ferroelectric polarization switching down to 100-picosecond in sub-60 mV/dec germanium ferroelectric nanowire FETs. In Symposium on VLSI Technology 89–90 (IEEE, 2018).

  10. 10.

    Yoo, H. K. et al. Engineering of ferroelectric switching speed in Si doped HfO2 for high-speed 1T-FERAM application. In Proceedings of IEEE International Electron Devices Meeting 481–484 (IEEE, 2017).

  11. 11.

    Dünkel, S. et al. A FeFET based super-low-power ultra-fast embedded NVM technology for 22 nm FDSOI and beyond. In Proceedings of IEEE International Electron Devices Meeting 485–488 (IEEE, 2017).

  12. 12.

    Si, M. et al. Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nat. Nanotechnol. 13, 24–29 (2018).

    Article  Google Scholar 

  13. 13.

    Si, M., Liao, P.-Y., Qiu, G., Duan, Y. & Ye, P. D. Ferroelectric field-effect transistors based on MoS2 and CuInP2S6 two-dimensional van der Waals heterostructure. ACS Nano 12, 6700–6705 (2018).

    Article  Google Scholar 

  14. 14.

    Mikolajick, T., Slesazeck, S., Park, M. H. & Schroeder, U. Ferroelectric hafnium oxide for ferroelectric random-access memories and ferroelectric field-effect transistors. MRS Bull. 43, 340–346 (2018).

    Article  Google Scholar 

  15. 15.

    Li, J. et al. Ultrafast polarization switching in thin-film ferroelectrics. Appl. Phys. Lett. 84, 1174–1176 (2004).

    Article  Google Scholar 

  16. 16.

    Larsen, P. K., Kampschöer, G. L. M., Ulenaers, M. J. E., Spierings, G. A. C. M. & Cuppens, R. Nanosecond switching of thin ferroelectric films. Appl. Phys. Lett. 59, 611–613 (1991).

    Article  Google Scholar 

  17. 17.

    Ross, I. M. Semiconductive translating device. US patent 2,791,760 (1957).

  18. 18.

    Ma, T. P. & Han, J. P. Why is nonvolatile ferroelectric memory field-effect transistor still elusive? IEEE Electron Device Lett. 23, 386–388 (2002).

    Article  Google Scholar 

  19. 19.

    Zhou, Y. et al. Out-of-plane piezoelectricity and ferroelectricity in layered α-In2Se3 nanoflakes. Nano Lett. 17, 5508–5513 (2017).

    Article  Google Scholar 

  20. 20.

    Ding, W. et al. Prediction of intrinsic two-dimensional ferroelectrics in In2Se3 and other III2–VI3 van der Waals materials. Nat. Commun. 8, 14956 (2017).

    Article  Google Scholar 

  21. 21.

    Cui, C. et al. Intercorrelated in-plane and out-of-plane ferroelectricity in ultrathin two-dimensional layered semiconductor In2Se3. Nano Lett. 18, 1253–1258 (2018).

    Article  Google Scholar 

  22. 22.

    Xiao, J. et al. Intrinsic two-dimensional ferroelectricity with dipole locking. Phys. Rev. Lett. 120, 227601 (2018).

    Article  Google Scholar 

  23. 23.

    Zheng, C. et al. Room temperature in-plane ferroelectricity in van der Waals In2Se3. Sci. Adv. 4, eaar7720 (2018).

    Article  Google Scholar 

  24. 24.

    Wan, S. et al. Room-temperature ferroelectricity and switchable diode effect in two-dimensional α-In2Se3 thin layers. Nanoscale 10, 14885–14892 (2018).

    Article  Google Scholar 

  25. 25.

    Xue, F. et al. Gate-tunable and multidirection-switchable memristive phenomena in a van der Waals ferroelectric. Adv. Mater. 31, 1901300 (2019).

    Article  Google Scholar 

  26. 26.

    Lin, M. et al. Controlled growth of atomically thin In2Se3 flakes by van der Waals epitaxy. J. Am. Chem. Soc. 135, 13274–13277 (2013).

    Article  Google Scholar 

  27. 27.

    Zhou, J. et al. Controlled synthesis of high-quality monolayered α-In2Se3 via physical vapor deposition. Nano Lett. 15, 6400–6405 (2015).

    Article  Google Scholar 

  28. 28.

    McClellan, C. J., Yalon, E., Smithe, K. K., Suryavanshi, S. V. & Pop, E. Effective n-type doping of monolayer MoS2 by AlOx. In 2017 75th Annual Device Research Conference (DRC) 7999392 (IEEE, 2017).

  29. 29.

    Qiu, G. et al. High-performance few-layer tellurium CMOS devices enabled by atomic layer deposited dielectric doping technique. In 2018 76th Annual Device Research Conference (DRC) 8442253 (IEEE, 2018).

  30. 30.

    Powell, M. J. Charge trapping instabilities in amorphous silicon–silicon nitride thin-film transistors. Appl. Phys. Lett. 43, 597–599 (1983).

    Article  Google Scholar 

  31. 31.

    Park, S. J. et al. Reconfigurable Si nanowire nonvolatile transistors. Adv. Electron. Mater. 4, 1700399 (2018).

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported in part by a NSF/AFOSR EFRI 2DARE programme and in part by ASCENT, one of six centres in JUMP, a Semiconductor Research Corporation (SRC) programme sponsored by DARPA. J.J. and H.W. acknowledge support from the US Office of Naval Research for the TEM effort at Purdue.

Author information

Affiliations

  1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA

    Mengwei Si, Atanu K. Saha, Gang Qiu, Jingkai Qin, Yuqin Duan, Chang Niu, Sumeet K. Gupta & Peide D. Ye

  2. Birck Nanotechnology Center, Purdue University, West Lafayette, IN, USA

    Mengwei Si, Shengjie Gao, Gang Qiu, Jingkai Qin, Yuqin Duan, Chang Niu, Wenzhuo Wu & Peide D. Ye

  3. School of Industrial Engineering, Purdue University, West Lafayette, IN, USA

    Shengjie Gao & Wenzhuo Wu

  4. School of Materials Science and Engineering, Purdue University, West Lafayette, IN, USA

    Jie Jian & Haiyan Wang

Authors
  1. Mengwei Si
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Atanu K. Saha
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Shengjie Gao
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Gang Qiu
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Jingkai Qin
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Yuqin Duan
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Jie Jian
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. Chang Niu
    View author publications

    You can also search for this author in PubMed Google Scholar

  9. Haiyan Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  10. Wenzhuo Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  11. Sumeet K. Gupta
    View author publications

    You can also search for this author in PubMed Google Scholar

  12. Peide D. Ye
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

P.D.Y. and M.S. conceived the idea and proposed the FeS-FET concept. M.S. carried out device fabrication, electrical measurements and analysis. A.K.S. and S.K.G. performed the numerical simulation. S.G. and W.W. performed PFM measurements. J.Q., J.J. and H.W. conducted the TEM and EDS measurements. Y.D. and M.S. carried out SEM imaging and EDS analysis. G.Q. obtained the Raman and photoluminescence measurements. G.Q. and C.N. performed the low-temperature I–V and Hall measurements. M.S. and P.D.Y. co-wrote the manuscript and all authors commented on it.

Corresponding author

Correspondence to Peide D. Ye.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Supplementary information

Supplementary Information

Supplementary sections 1–8.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Si, M., Saha, A.K., Gao, S. et al. A ferroelectric semiconductor field-effect transistor. Nat Electron 2, 580–586 (2019). https://doi.org/10.1038/s41928-019-0338-7

Download citation

Further reading

Search

Advanced search

Quick links