Two-dimensional semiconductors could be used as a channel material in low-power transistors, but the deposition of high-quality, ultrathin high-κ dielectrics on such materials has proved challenging. In particular, atomic layer deposition typically leads to non-uniform nucleation and island formation, creating a porous dielectric layer that suffers from current leakage, particularly when the equivalent oxide thickness is small. Here, we report the atomic layer deposition of high-κ gate dielectrics on two-dimensional semiconductors using a monolayer molecular crystal as a seeding layer. The approach can be used to grow dielectrics with an equivalent oxide thickness of 1 nm on graphene, molybdenum disulfide (MoS2) and tungsten diselenide (WSe2). Compared with dielectrics created using established methods, our dielectrics exhibit a reduced roughness, density of interface states and leakage current, as well as an improved breakdown field. With the technique, we fabricate graphene radio-frequency transistors that operate at 60 GHz, and MoS2 and WSe2 complementary metal–oxide–semiconductor transistors with a supply voltage of 0.8 V and subthreshold swing down to 60 mV dec−1. We also create MoS2 transistors with a channel length of 20 nm, which exhibit an on/off ratio of over 107.
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The data that support the plots within this paper and other findings of this study are available from the corresponding author on reasonable request.
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This work is supported by National Natural Science Foundation of China grants 61734003, 61521001, 61851401, 51861145202, 61861166001, 11874199 and 21872100; National Key Basic Research Programme of China grants 2015CB921600 and 2015CB654901; Natural Science Foundation of Jiangsu Province grants BK20170005; Singapore MOE grant R143-000-A43-114; Programme A for Outstanding Ph.D. candidate of Nanjing University 201801A013; Postgraduate Research & Practice Innovation Programme of Jiangsu Province KYCX18_0045; Strategic Priority Research Programme of Chinese Academy of Sciences XDB 30000000; a Grant-in-Aid for JSPS Research Fellows from the JSPS KAKENHI; the JSPS A3 Foresight Programme and JSPS KAKENHI grants JP19H00755 and 19K21956, Japan; Key Laboratory of Advanced Photonic and Electronic Materials, Collaborative Innovation Centre of Solid-State Lighting and Energy-Saving Electronics, and the Fundamental Research Funds for the Central Universities, China.
The authors declare no competing interests.
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Li, W., Zhou, J., Cai, S. et al. Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices. Nat Electron 2, 563–571 (2019). https://doi.org/10.1038/s41928-019-0334-y
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