Metal–oxide memristive integrated technologies for analogue neuromorphic computing have undergone notable developments in the past decade, but are still not mature enough for very large-scale integration with complementary metal–oxide–semiconductor (CMOS) processes. Although non-volatile floating-gate synapse transistors are a more advanced technology embedded within CMOS processes, their performance as analogue resistive memories remains limited. Here, we report a low-power, two-terminal floating-gate transistor fabricated using standard single-poly technology in a commercial 180 nm CMOS process. Our device, which is integrated with a readout transistor, can operate in an energy-efficient subthreshold memristive mode. At the same time, it is linearized for small-signal changes with a two-orders-of-magnitude resistance dynamic range. Our device can be precisely tuned using optimized switching voltages and times, and can achieve 65 distinct resistive levels and ten-year analogue data retention. We experimentally demonstrate the feasibility of a selector-free integrated memristive array in basic neuromorphic applications, including spike-time-dependent plasticity, vector-matrix multiplication, associative memory and classification training.
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This research was partially supported by the Israeli Planning and Budgeting Committee Fellowship, by the Israel Ministry of Economics KAMIN project no. 57681, by the Andrew and Erna Finci Viterbi Graduate Fellowship and by the European Research Council under the European Union’s Horizon 2020 Research and Innovation Programme under agreement no. 757259.
The authors declare no competing interests.
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Danial, L., Pikhay, E., Herbelin, E. et al. Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing. Nat Electron 2, 596–605 (2019). https://doi.org/10.1038/s41928-019-0331-1
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