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Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing

Nature Electronics volume 2, pages 596–605 (2019)Cite this article

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Abstract

Metal–oxide memristive integrated technologies for analogue neuromorphic computing have undergone notable developments in the past decade, but are still not mature enough for very large-scale integration with complementary metal–oxide–semiconductor (CMOS) processes. Although non-volatile floating-gate synapse transistors are a more advanced technology embedded within CMOS processes, their performance as analogue resistive memories remains limited. Here, we report a low-power, two-terminal floating-gate transistor fabricated using standard single-poly technology in a commercial 180 nm CMOS process. Our device, which is integrated with a readout transistor, can operate in an energy-efficient subthreshold memristive mode. At the same time, it is linearized for small-signal changes with a two-orders-of-magnitude resistance dynamic range. Our device can be precisely tuned using optimized switching voltages and times, and can achieve 65 distinct resistive levels and ten-year analogue data retention. We experimentally demonstrate the feasibility of a selector-free integrated memristive array in basic neuromorphic applications, including spike-time-dependent plasticity, vector-matrix multiplication, associative memory and classification training.

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Fig. 1: Y-flash non-volatile memory device.
Fig. 2: Y-flash memristive device.
Fig. 3: Y-flash memristive synapses.
Fig. 4: Associative memory of a Y-flash memristive neural network.
Fig. 5: Training and classification of a Y-flash memristive neural network.

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Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

Code availability

The computer codes used in this study are available within this paper and its Supplementary Information files.

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Acknowledgements

This research was partially supported by the Israeli Planning and Budgeting Committee Fellowship, by the Israel Ministry of Economics KAMIN project no. 57681, by the Andrew and Erna Finci Viterbi Graduate Fellowship and by the European Research Council under the European Union’s Horizon 2020 Research and Innovation Programme under agreement no. 757259.

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Authors and Affiliations

  1. Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion – Israel Institute of Technology, Haifa, Israel

    Loai Danial, Eric Herbelin, Nicolas Wainstein, Vasu Gupta, Nimrod Wald & Shahar Kvatinsky

  2. TowerJazz, Migdal HaEmek, Israel

    Evgeny Pikhay & Yakov Roizin

  3. Department of Biomedical Engineering, Technion – Israel Institute of Technology, Haifa, Israel

    Ramez Daniel

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  1. Loai Danial
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Contributions

L.D., Y.R., R.D. and S.K. designed the study. L.D., E.H. and E.P. performed experiments and collected data. E.P. and Y.R. invented the Y-flash memristive structure and L.D., R.D. and S.K. invented the subthreshold small-signal memristive operation mode. L.D. developed models and executed simulations. All authors analysed the data, discussed the results and wrote the manuscript.

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Correspondence to Shahar Kvatinsky.

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Supplementary Sections 1–6 and Tables 1–10.

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Danial, L., Pikhay, E., Herbelin, E. et al. Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing. Nat Electron 2, 596–605 (2019). https://doi.org/10.1038/s41928-019-0331-1

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