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Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process


The performance of silicon complementary metal–oxide–semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of additional device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit containing 100-nm-node fin field-effect transistors using an in-air solution process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.

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Fig. 1: Monolithic integration of AOS thin-film devices on silicon CMOSs.
Fig. 2: HV AOS inverter by MESFET integration with MISFET.
Fig. 3: HV AOS V-TFD with LV switching.
Fig. 4: Interface analysis of top Schottky contact and bottom ohmic contact.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author on reasonable request.


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We thank G. A. Torres Sevilla and M. M. Hussain of King Abdullah University of Science and Technology for providing the silicon CMOS samples. We also gratefully acknowledge the contributions of W. Hu, J. Li and J. Miller to TFT fabrication. This work was supported by SPAWAR through DARPA Young Faculty Award N66001-14-1-4046 under D. Green and Y.-K. Chen. Any opinions, findings, conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of DARPA or SPAWAR. Y.S. was supported in part by the Kwanjeong Educational Foundation. Portions of the work reported here were performed in the Lurie Nanofabrication Facility and Michigan Center for Materials Characterization, which are supported by the University of Michigan’s College of Engineering.

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R.L.P. led the project and supervised Y.S., B.F. and Y.Z. Y.S. conducted the design and fabrication of MISFET, MESFET and V-TFD devices and performed IV and CV measurements, stress tests and charge transport analysis. Y.S. conducted the design, development and measurement of the inverters and rectifiers, including the test setup. Y.S. performed the TEM, EDS and XPS characterization. Y.S. and R.L.P. both contributed to the preparation of the manuscript. B.F. fabricated the MISFETs on silicon CMOS ICs and tested them. Y.Z. conducted the thermal budget test of the silicon finFETs.

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Correspondence to Rebecca L. Peterson.

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Supplementary Information

Supplementary Sections 1–10, Supplementary Figs. 1–10 and Supplementary Tables 1–5.

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Son, Y., Frost, B., Zhao, Y. et al. Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process. Nat Electron 2, 540–548 (2019).

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