The imaging of integrated circuits across different length scales is required for failure analysis, design validation and quality control. At present, such inspection is accomplished using a hierarchy of different probes, from optical microscopy on the millimetre length scale to electron microscopy on the nanometre scale. Here we show that ptychographic X-ray laminography can provide non-destructive, three-dimensional views of integrated circuits, yielding both images of an entire chip volume and high-resolution images of arbitrarily chosen subregions. We demonstrate the approach using chips produced with 16 nm fin field-effect transistor technology, achieving a reconstruction resolution of 18.9 nm, and compare our results with photolithographic mask layout files and more conventional imaging approaches such as scanning electron microscopy. The technique should also be applicable to other branches of science and engineering where three-dimensional X-ray images of planar samples are required.
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The aligned laminography projections generated during the current study are available under the Creative Common license in the Zenodo repository, https://doi.org/10.5281/zenodo.2657340.
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The measurements were performed at the cSAXS beamline of the Swiss Light Source at the Paul Scherrer Institut.
The authors declare no competing interests.
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Holler, M., Odstrcil, M., Guizar-Sicairos, M. et al. Three-dimensional imaging of integrated circuits with macro- to nanoscale zoom. Nat Electron 2, 464–470 (2019). https://doi.org/10.1038/s41928-019-0309-z
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